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73S1215F-68IMR/F 参数 Datasheet PDF下载

73S1215F-68IMR/F图片预览
型号: 73S1215F-68IMR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 80515系统级芯片, USB , ISO 7816 / EMV ,密码键盘和更多 [80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More]
分类和应用: 多功能外围设备微控制器和处理器外围集成电路时钟
文件页数/大小: 136 页 / 1028 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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DS_1215F_003  
73S1215F Data Sheet  
The master clock control register enables different sections of the clock circuitry and specifies the value  
of the VCO Mcount divider. The MCLK must be configured to operate at 96MHz to ensure proper  
operation of some of the peripheral blocks according to the following formula:  
MCLK = (Mcount * 2 + 4) * FXTAL = 96MHz  
Mcount is configured in the MCLKCtl register must be bound between a value of 1 to 7. The possible  
crystal or external clock frequencies for getting MCLK = 96MHz are shown in Table 12.  
Table 12: Frequencies and Mcount Values for MCLK = 96MHz  
FXTAL (MHz)  
12.00  
9.60  
Mcount (N)  
2
3
4
5
6
8.00  
6.86  
6.00  
Master Clock Control Register (MCLKCtl): 0x8F Å 0x0A  
Table 13: The MCLKCtl Register  
MSB  
LSB  
HSOEN KBEN SCEN USBEN 32KEN MCT.2 MCT.1 MCT.0  
Bit  
Symbol  
Function  
High-speed oscillator disable. When set = 1, disables the high-speed crystal  
oscillator and VCO/PLL system. Do not set this bit = 1.  
MCLKCtl.7  
HSOEN  
MCLKCtl.6  
MCLKCtl.5  
MCLKCtl.4  
KBEN  
SCEN  
1 = Disable the keypad logic clock.  
1 = Disable the smart card logic clock.  
1 = Disable the USB logic clock.  
USBEN  
1 = Disable the 32Khz oscillator. When the 32kHz oscillator is enabled, the  
RTC and other circuits such as debounce clocks are clocked using the  
32kHz oscillator output. When disabled, the main oscillator provides the  
32kHz clock for the RTC and other circuits. Note: This bit must be set if  
there is no 32KHz crystal or the 44 pin package is used. Some internal  
clocks and circuits will not run if the oscillator is enabled and no  
crystal is connected.  
MCLKCtl.3  
32KEN  
MCLKCtl.2  
MCLKCtl.1  
MCT.2  
MCT.1  
This value determines the ratio of the VCO frequency (MCLK) to the high-  
speed crystal oscillator frequency such that:  
MCLK = (MCount*2 + 4)* FXTAL. The default value is MCount = 2h such that  
MCLK = (2*2 + 4)*12.00MHz = 96MHz.  
MCLKCtl.0  
MCT.0  
The MPU clock that drives the CPU core defaults to 3.6923MHz after reset. The MPU clock is scalable  
by configuring the MPU Clock Control register (MPUCKCtl).  
Rev. 1.4  
25  
 
 
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