73S1215F Data Sheet
DS_1215F_003
MPU Clock Control Register (MPUCKCtl): 0xFFA1 Å 0x0C
Table 14: The MPUCKCtl Register
MSB
LSB
–
–
MDIV.5 MDIV.4 MDIV.3 MDIV.2 MDIV.1 MDIV.0
Bit
Symbol
Function
MPUCKCtl.7
MPUCKCtl.6
MPUCKCtl.5
MPUCKCtl.4
MPUCKCtl.3
MPUCKCtl.2
MPUCKCtl.1
MPUCKCtl.0
–
–
MDIV.5
MDIV.4
MDIV.3
MDIV.2
MDIV.1
MDIV.0
This value determines the ratio of the MPU master clock frequency to
the VCO frequency (MCLK) such that
MPUClk = MCLK/(2 * (MPUCKDiv(5:0) + 1)).
Do not use values of 0 or 1 for MPUCKDiv(n).
Default is 0Ch to set CPCLK = 3.6923MHz.
The oscillator circuits are designed to connect directly to standard parallel resonant crystal in a Pierce
oscillator configuration. Each side of the crystal should include a 22pF capacitor to ground for both
oscillator circuits and a 1MΩ resistor is required across the 12MHz crystal.
The CPU clock is available as an output on pin CPUCLK (68-pin version only).
73S1215F
1MΩ
12MHz
32KHz
22pF
22pF
22pF
22pF
Note: The crystals should be placed as close as possible to the IC, and vias should be avoided.
Figure 4: Oscillator Circuit
26
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
