73S1215F Data Sheet
Fi code
DS_1215F_003
Table 101: Divider Values for the ETU Clock
0000
372
0001
372
0010
558
0011
744
0100
1116
0101
1488
Di
code
F→
D↓
1
0001
0010
0011
0100
1000
0101
1001
0110
744
372
186
93
744
372
186
93
1116
558
279
138
93
1488
744
372
186
124
93
2232
1116
558
279
186
140
112
70
2976
1488
744
372
248
186
149
93
2
4
8
12
16
20
32
62
62
47
47
70
37
37
56
74
23
23
35
47
Fi code
F→
D↓
1
0110
1860
1001
512
1010
768
1011
1024
1100
1536
1101
2048
Di
code
0001
0010
0011
0100
1000
0101
1001
0110
3720
1860
930
465
310
233
186
116
1024
512
256
128
85
1536
768
384
192
128
96
2048
1024
512
256
171
128
102
64
3072
1536
768
384
256
192
154
96
4096
2048
1024
512
2
4
8
12
16
20
32
341
64
256
51
77
205
32
48
128
Table 102: The FDReg Bit Functions
Function
Bit
Symbol
FDReg.7
FDReg.6
FDReg.5
FDReg.4
FDReg.3
FDReg.2
FDReg.1
FDReg.0
FVAL.3
FVAL.2
FVAL.1
FVAL.0
DVAL.3
DVAL.2
DVAL.1
DVAL.0
Refer to Table 101 above. This value is converted per the table to set the
divide ratio used to generate the baud rate (ETU). Default, also used for
ATR, is 0001 (Fi = 372). This value is used by the selected interface.
Refer to Table 101 above. This value is used to set the divide ratio used to
generate the smart card CLK. Default, also used for ATR, is 0001 (Di = 1).
104
Rev. 1.4
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
