DS_1215F_003
73S1215F Data Sheet
FD Control Register (FDReg): 0xFE13 Å 0x11
This register uses the transmission factors F and D to set the ETU (baud) rate. The values in this register
are mapped to the ISO 7816 conversion factors as described below. The CLK signal for each interface is
created by dividing a high-frequency, intermediate signal (MSCLK) by 2. The ETU baud rate is created
by dividing MSCLK by 2 times the Fi/Di ratio specified by the codes below. For example, if FI = 0001 and
DI = 0001, the ratio of Fi/Di is 372/1. Thus the ETU divider is configured to divide by 2 * 372 = 744. The
maximum supported F/D ratio is 4096.
Table 99: The FDReg Register
MSB
FVAL.3
LSB
DVAL.0
FVAL.2
FVAL.1
FVAL.0
DVAL.3
DVAL.2
DVAL.1
Table 100: Divider Ratios Provided by the ETU Counter
FI (code)
Fi (ratio)
0000
372
4
0001
372
5
0010
558
6
0011
744
8
0100
1116
12
0101
1488
16
0110
0111
1860
20
1860⊕
20⊕
FCLK max
FI(code)
Fi(ratio)
1000
512⊕
5⊕
1001
512
5
1010
768
7.5
1011
1024
10
1100
1536
15
1101
2048
20
1110
2048⊕
20⊕
1111
2048⊕
20⊕
FCLK max
DI(code)
Di(ratio)
0000
0001
1
0010
2
0011
4
0100
8
0101
16
0110
32
0111
1⊕
32⊕
DI(code)
Di(ratio)
1000
12
1001
20
1010
1011
1100
1101
1110
1111
16⊕
16⊕
16⊕
16⊕
16⊕
16⊕
Note: values marked with ⊕ are not included in the ISO definition and arbitrary values have been
assigned.
The values given below are used by the ETU divider to create the ETU clock. The entries that are not
shaded will result in precise CLK/ETU per ISO requirements. Shaded areas are not precise but are
within 1% of the target value.
Rev. 1.4
103
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
