Data Sheet 71M6531D/F-71M6532D/F
FDS 6531/6532 005
IRCON[1]
IRCON[0]
IEX2
1 = External interrupt 2 occurred and has not been cleared.
Not used.
–
TF0 and TF1 (Timer 0 and Timer 1 overflow flags) will be automatically cleared by hardware when
the service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service
routine is called).
External MPU Interrupts
The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in
other parts of the 71M6531D/F or 71M6532D/F, for example the CE, DIO, RTC or EEPROM interface.
The external interrupts are connected as described in Table 30. The polarity of interrupts 2 and 3 is
programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should be
programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts
4 through 6 are defined as rising-edge sensitive. Thus, the hardware signals attached to interrupts 5 and
6 are inverted to achieve the edge polarity shown in Table 30.
Table 30: External MPU Interrupts
External
Interrupt
Connection
Polarity
Flag Reset
0
1
2
3
4
5
6
Digital I/O High Priority
see Section 1.5.7 automatic
see Section 1.5.7 automatic
Digital I/O Low Priority
FWCOL0, FWCOL1, SPI
CE_BUSY
falling
falling
rising
falling
automatic
automatic
automatic
automatic
manual
PLL_OK (rising), PLL_OK (falling)
EEPROM busy
XFER_BUSY, RTC_1SEC or WD_NROVF falling
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See Section
1.5.7 Digital I/O for more information.
FWCOLx interrupts occur when the CE collides with a flash write attempt. See the Flash Write description
in the Flash Memory section for more detail.
SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its
own flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler.
XFER_BUSY, RTC_1SEC, WD_NROVF, FWCOL0, FWCOL1, SPI, PLLRISE and PLLFALL have their
own enable and flag bits in addition to the interrupt 6, 4 and enable and flag bits (see Table 31).
IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other
flags, IE_XFER through IE_PB, are cleared by writing a zero to them.
Since these bits are in an SFR bit addressable byte, common practice would be to clear them
with a bit operation, but this must be avoided. The hardware implements bit operations as a
byte-wide read-modify-write hardware macro. If an interrupt occurs after the read, but before
the write, its flag will be cleared unintentionally.
The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a
zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore
ones written to them.
Table 31: Interrupt Enable and Flag Bits
Interrupt Enable
Name Location
Interrupt Flag
Name Location
Interrupt Description
EX0
EX1
EX2
EX3
SFR A8[0]
SFR A8[2]
SFR B8[1]
SFR B8[2]
IE0
SFR 88[1]
SFR 88[3]
SFR C0[1]
SFR C0[2]
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
IE1
IEX2
IEX3
32
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