71M6533/71M6534 Data Sheet
FDS_6533_6534_004
MUX_DIV[3:0]
MUX_SYNC_E
OPT_FDC[1:0]
209D[3:0]
2020[7]
0
0
0
0
0
0
R/W The number of states in the input multiplexer.
R/W When set, SEG7 outputs MUX_SYNC. Otherwise, SEG7 is an LCD pin.
R/W Selects the modulation duty cycle for OPT_TX.
2007[1:0]
OPT_FDC[1:0]
Function
50% Low
25% Low
12.5% Low
6.25% Low
00
01
10
11
OPT_RXDIS
2008[5]
0
0
R/W Configures OPT_RX to an analog input to the optical UART comparator or as a digital
input/output, DIO1.
0 = OPT_RX, 1 = DIO1.
OPT_RXINV
2008[4]
0
0
R/W Inverts the result from the OPT_RX comparator when 1. Affects only the UART input.
Has no effect when OPT_RX is used as a DIO input.
OPT_TXE[1:0]
2007[7:6]
00
00
R/W Configures the OPT_TX output pin.
OPT_TXE[1:0]
Function
OPT_TX
DIO2
WPULSE
RPULSE
00
01
10
11
OPT_TXINV
2008[0]
2008[1]
0
0
0
0
R/W Inverts OPT_TX when 1. This inversion occurs before modulation.
OPT_TXMOD
R/W Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated
when it would otherwise have been zero. The modulation is applied after any inver-
sion caused by OPT_TXINV.
PLL_OK
2003[6]
0
0
R
Indicates that system power is present and the clock generation PLL is settled.
PLS_MAXWIDTH 2080[7:0]
[7:0]
FF
FF
R/W Determines the maximum width of the pulse (low going pulse).
The maximum pulse width is (2*PLS_MAXWIDTH + 1)*TI. Where TI is PLS_INTERVAL.
If PLS_INTERVAL = 0, TI is the sample time (397 µs). If set to 255, pulse width control
is disabled and pulses are output with a 50% duty cycle.
PLS_INTERVAL 2081[7:0]
[7:0]
0
0
R/W For PULSE_W and PULSE_V only, if the FIFO is used, PLS_INTERVAL must be set to
81. If PLS_INTERVAL = 0, the FIFO is not used and pulses are output as soon as the
CE issues them.
PLS_INV
2004[6]
0
–
0
–
R/W Inverts the polarity of the pulse outputs Normally, these pulses are active low. When
inverted, they become active high.
PREBOOT
SFRB2[7]
R
Indicates that the preboot sequence is active.
86
© 2007-2009 TERIDIAN Semiconductor Corporation
v1.1