FDS_6533_6534_004
71M6533/71M6534 Data Sheet
R/W Selects the temperature trim fuse to be read with the TRIM register:
TRIMSEL[3:0]
20FD[3:0]
0
0
0
0
TRIMSEL[3:0]
Trim Fuse
TRIMT[7:0]
TRIMM[2:0]
TRIMBGA
TRIMBGB
Purpose
1
4
5
6
Trim for the magnitude of VREF
Trim values related to temperature com-
pensation
TRIM[7:0]
20FF
R/W Contains TRIMBGA,TRIMBGB or TRIMM[2:0] depending on the value written to
TRIMSEL[3:0]. If TRIMBGB = 0, the device is a 71M6533/71M6534, else it is a
71M6533H/71M6534H.
UMUX_E*
200F[7]
S00F[6]
0
0
0
0
R/W Enables the optical UART multiplexer, selects the alternate function (MTX, MRX) for
DIO8, DIO9.
UMUX_SEL*
R/W When UMUX_E = 1, selects between OPT_TX, OPT_RX and MTX, MRX as the optical
UART I/O pins. 0 = OPT_TX, OPT_RX, 1 = MTX, MRX
VB_REF
2005[6]
2005[7]
0
0
0
0
R/W Configures the ADC so that VB is the zero reference.
VDDREGZ
R/W When zero, changes the input reference of the ADC to V3P3A for the IA, IB, VA and
VB inputs. Otherwise, the reference is VBIAS.
–
–
–
–
VERSION[7:0]
2006
20C8
R
R
The device version index. This word may be read by the firmware to determine the
silicon version.
VERSION[7:0] Silicon Version
0000 0101
A05
VREF_CAL
VREF_DIS
WAKE_ARM
2004[7]
2004[3]
20A9[7]
0
0
0
0
0
–
R/W Brings VREF to the VREF pad. This feature is disabled when VREF_DIS =1.
R/W Disables the internal voltage reference.
Writing a 1 to this bit arms the autowake timer and presets it with the values presently
in WAKE_PRD and WAKE_RES. The autowake timer is reset and disarmed whenever
the processor is in MISSION mode or BROWNOUT mode. The timer must be armed
at least three RTC cycles before the SLEEP or LCD-ONLY mode is commanded.
W
–
WAKE_PRD
WAKE_RES
20A9[2:0]
001
R/W Sleep time. Time = WAKE_PRD[2:0]*WAKE_RES. The default = 001. The maximum
value is 7.
–
0
20A9[3]
20B1[0]
0
–
R/W Resolution of WAKE timer: 1 = 1 minute, 0 = 2.5 seconds.
WD_NROVF_
FLAG
R/W This flag is set approximately 1 ms before the watchdog timer overflows. It is cleared
by writing a 0 or on the falling edge of WAKE.
WD_RST
SFR F8[7]
0
0
W
WD timer bit. This bit must be accessed with byte operations. Operations possible for
this bit are:
Write 0: Clears the flag.
Write 1: Resets the WDT.
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
89
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
