FDS_6533_6534_004
71M6533/71M6534 Data Sheet
L
L
LCD_BITMAP
[50:48]
2026[2:0]
0
0
R/W Configuration for DIO30/SEG50 through DIO28/SEG48. LCD_BITMAP[48] correspond-
ing to DIO28/SEG48 is only applicable to the 71M6534. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin.
LCD_BITMAP
[63:61],
[59:56]*
2027[7:5,3:0]
2028[7:0]
R/W Configuration for DIO43/SEG63 through DIO41/SEG61 and DIO39/SEG59 through
DIO36/SEG56. LCD_BITMAP[62] corresponding to DIO42/SEG62 and
LCD_BITMAP[59:56] corresponding to DIO39/SEG59 through DIO36/SEG56 are only
applicable to the 71M6534. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin.
L
LCD_BITMAP
[71:64]
0
R/W Configuration for DIO51/SEG71 through DIO44/SEG64. LCD_BITMAP[66] correspond-
ing to DIO46/SEG66 is only applicable to the 71M6534. Unused bits should be set to zero.
1 = LCD pin, 0 = DIO pin.
L
L
LCD_BLKMAP18 205A[3:0]
[3:0]
0
0
R/W Identifies which segments connected to SEG18 should blink. 1 means blink. The
most significant bit corresponds to COM3, the least significant bit to COM0.
LCD_CLK[1:0]
2021[1:0]
20AB[3:1]
R/W Sets the LCD clock frequency for the COM/SEG pins (not the frame rate) according to
the following (fw = 32768 Hz):
00 = fw/512, 01 = fw/256, 10 = fw/128, 11 = fw/64
L
LCD_DAC[2:0]
0
R/W LCD contrast control DAC. Adjusts the LCD voltage in steps of 0.2 V from V3P3SYS
(mission mode) or VBAT (brownout/LCD modes).
LCD_DAC[2:0]
Resulting LCD Voltage
V3P3 or VBAT
000
001
010
011
100
101
110
111
V3P3 or VBAT – 0.2V
V3P3 or VBAT – 0.4V
V3P3 or VBAT – 0.6V
V3P3 or VBAT – 0.8V
V3P3 or VBAT – 1.0V
V3P3 or VBAT – 1.2V
V3P3 or VBAT – 1.4V
L
LCD_E
2021[5]
0
R/W Enables the LCD display. When disabled, VLC2, VLC1 and VLC0 are ground as are
the COM and SEG outputs.
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
83
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
