FDS_6533_6534_004
71M6533/71M6534 Data Sheet
LCD_SEG63[3:0] 2045[7:4]
0
…
0
L
…
L
R/W
…
…
LCD_SEG65[3:0] 2047[7:4]
LCD_SEG66[3:0]* 2048[7:4]
LCD_SEG67[3:0] 2049[7:4]
0
L
R/W
0
…
0
L
…
L
R/W LCD Segment Data continued.
…
…
LCD_SEG71[3:0] 204D[7:4]
LCD_SEG72[3:0]* 204E[7:4]
0
…
0
L
…
L
R/W
…
…
LCD_SEG75[3:0]* 2051[7:4]
LCD_Y
2021[6]
0
L
R/W LCD Blink Frequency (ignored if blink is disabled or if the segment is off).
0 = 1 Hz (500 ms ON, 500 ms OFF)
1 = 0.5 Hz (1 s ON, 1 s OFF)
M26MHZ
M40MHZ
2005[4]
2005[0]
0
0
0
0
R/W M26MHZ and M40MHZ set the master clock (MCK) frequency. These bits are reset on
chip reset and may only be set. Attempts to write zeroes to M40MHZ and M26MHZ are
R/W
ignored.
M40MHZ M26MHZ MCK Frequency
0
0
1
1
0
1
0
1
20 MHz
26.7 MHz
40 MHz
40 MHz
MPU_DIV[2:0]
2004[2:0]
0
0
R/W The MPU clock divider (from MCK). These bits may be programmed by MPU without
risk of losing control.
MPU_DIV[2:0]
Resulting Clock Frequency
MCK/4
MCK/8
MCK/16
MCK/32
MCK/64
MCK/128
MCK/265
MCK/265
000
001
010
011
100
101
110
111
MUX_ALT
2005[2]
0
0
R/W The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an
alternate set of inputs.
If CHOP_E is 00, MUX_ALT is automatically asserted once per sum cycle, when
XFER_BUSY falls.
v1.1
© 2007-2009 TERIDIAN Semiconductor Corporation
85
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
