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71M6533H-IGTR/F 参数 Datasheet PDF下载

71M6533H-IGTR/F图片预览
型号: 71M6533H-IGTR/F
PDF下载: 下载PDF文件 查看货源
内容描述: 电能计量IC [Energy Meter IC]
分类和应用:
文件页数/大小: 124 页 / 1997 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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71M6533/71M6534 Data Sheet  
FDS_6533_6534_004  
DIO_0[7:0]  
DIO_1[7:0]  
DIO_2[7:0]  
DIO_3[6:0]  
SFR 80  
SFR 90  
SFR A0  
SFR B0  
0
0
0
0
The value on the DIO pins. Pins configured as LCD will read zero. The MPU writes to  
these registers to change the data on pins configured as outputs. Pins configured as LCD  
or input will ignore writes.  
R/W  
DIO_0[7:0] corresponds to DIO7 through DIO1 and PB (PB is read on DIO_0[0]).  
DIO_1[7:0] corresponds to DIO15 through DIO8. (DIO_1[4] corresponding to  
DIO12 is only applicable to the 71M6534)  
DIO_2[7:0] corresponds to DIO23 through DIO16. (DIO_2[4] corresponding to  
DIO22 is only applicable to the 71M6534)  
DIO_3[6:0] corresponds to DIO30 through DIO24. (DIO_3[4] corresponding to  
DIO28 is only applicable to the 71M6534)  
DIO_EEX[1:0]  
2008[7:6]  
0
0
R/W When set, converts DIO4 and DIO5 to interface with external EEPROM. DIO4 be-  
comes SDCK and DIO5 becomes bi-directional SDATA.  
DIO_EEX[1:0]  
Function  
00  
01  
10  
11  
Disable EEPROM interface  
2-Wire EEPROM interface  
3-Wire EEPROM interface  
--not used--  
DIO_PV  
2008[2]  
2008[3]  
200F[3]  
200F[2]  
SFR 9E  
SFR 9F  
2005[5]  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W Causes VARPULSE to be output on DIO7.  
R/W Causes WPULSE to be output on DIO6.  
R/W Causes XPULSE to be output on DIO8.  
R/W Causes YPULSE to be output on DIO9.  
R/W Serial EEPROM interface data.  
DIO_PW  
DIO_PX  
DIO_PY  
EEDATA[7:0]  
EECTRL[7:0]  
ECK_DIS  
R/W Serial EEPROM interface control.  
R/W Emulator clock disable. When ECK_DIS = 1, the emulator clock is disabled.  
If ECK_DIS is set, the emulator and programming devices will be unable to  
erase or program the device.  
EQU[2:0]  
2000[7:5]  
0
0
R/W Specifies the power equation to be used by the CE.  
EX_XFR  
EX_RTC  
EX_FWCOL  
EX_PLL  
2002[0]  
2002[1]  
2007[4]  
2007[5]  
0
0
0
0
0
0
0
0
R/W  
Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, the Firm-  
WareCollision (FWCOL), and PLL interrupts. Note that if one of these interrupts is to  
be enabled, its corresponding MPU EX enable must also be set. See Section 1.3.9  
Interrupts for details.  
80  
© 2007-2009 TERIDIAN Semiconductor Corporation  
v1.1