71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
Temperature Compensation
Internal Compensation: The internal voltage reference is calibrated during device manufacture. Trim data is stored in on-chip
fuses.
For the 71M6511, the temperature coefficients TC1 and TC2 are given as constants that represent typical component
behavior.
For the 71M6511H, the temperature characteristics of the chip are measured during production and then stored in the fuse
registers TRIMBGA, TRIMBGB and TRIMM[2:0]. TC1 and TC2 can be derived from the fuses by using the relations given in
the Electrical Specifications section. TC1 and TC2 can be further processed to generate the coefficients PPMC and PPMC2.
TRIMM[2:0], TRIMBGA and TRIMBGB are read by first writing either 4, 5 or 6 to TRIMSEL (0x20FD) and then reading the
value of TRIM (0x20FF).
When the EXT_TEMP register in CE DRAM (address 0x38) is set to 0, the CE automatically compensates for temperature
errors by controlling the GAIN_ADJ register (address 0x2E) based on the PPMC, PPMC2, and TEMP_X register values. In the
case of internal compensation, GAIN_ADJ is an output of the CE.
External Compensation: Rather than internally compensating for the temperature variation, the bandgap temperature is
provided to the embedded MPU, which then may digitally compensate the power outputs. This permits a system-wide
temperature correction over the entire system rather than local to the chip. The incorporated thermal coefficients may include
the current sensors, the voltage sensors, and other influences. Since the band gap is chopper stabilized via the CHOP_EN
bits, the most significant long-term drift mechanism in the voltage reference is removed.
When the EXT_TEMP register in CE DRAM is set to 15, the CE ignores the PPMC, PPMC2, and TEMP_X register values and
applies the gain supplied by the MPU in GAIN_ADJ. External compensation enables the MPU to control the CE gain based on
any variable, and when EXT_TEMP = 15, GAIN_ADJ is an input to the CE.
Chopping Circuitry
As explained in the hardware section, the bits of the I/O RAM register CHOP_ENA[1:0] have to be toggled in between
multiplexer cycles to achieve the desired elimination of DC offset.
The amplifier within the reference is auto-zeroed by means of an internal signal that is controlled by the CHOP_EN bits. When
this signal is HIGH, the connection of the amplifier inputs is reversed. This preserves the overall polarity of the amplifier gain
but inverts the input offset. By alternately reversing the connection, the offset of the amplifier is averaged to zero. The two bits
of the CHOP_EN register have the function specified in Table 61.
CHOP_EN[1]
CHOP_EN[0]
Function
0
0
1
1
0
1
0
1
Toggle chop signal
Reference connection positive
Reference connection reversed
Toggle chop signal
Table 61: CHOP_EN Bits
For automatic chopping, the CHOP_EN bits are set to either 00 or 11. In this mode, the polarity of the signals feeding the
reference amplifier will be automatically toggled for each multiplexer cycle as shown in Figure 21. With an even number of
multiplexer cycles in each accumulation interval, the number of cycles with positive reference connection will equal the number
of cycles with reversed connection, and the offset for each sampled signal will be averaged to zero. This sequence is
acceptable when only the primary signals (meter voltage, meter current) are of interest.
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