71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
PULSES
W (DIO6)
VAR (DIO7)
DISPLAY (me-
mory-mapped
LCD segments)
APULSEW
APULSER
SERIAL
EXT_PULSE
(UART0/1)
MPU
DATA
EEPROM
(I2C)
SAMPLES
ADC
CE_BUSY
XFER_BUSY
DIO
CE
Mux Ctrl.
INTERRUPTS
I/O RAM (CONFIGURATION RAM)
Figure 18: MPU/CE Communication (Functional)
The MPU will wait for the CE to signal that fresh data is ready (the XFER interrupt). It will read the data and perform additional
processing such as energy accumulation.
CE PRAM
FLASH
CE_EN
COMPUTATION
ENGINE
XFER Interrupt
CE DRAM
MPU
Figure 19: MPU/CE Communication (Processing Sequence)
Fault, Reset, Power-Up
Reset Mode: When the RESETZ pin is pulled low or when V1 < VBIAS, all digital activity in the chip stops while analog circuits
are still active. The oscillator and RTC module continue to run. Additionally, all I/O RAM bits are cleared. As long as V1, the
input voltage at the power fault block, is greater than VBIAS, the internal 2.5V regulator will continue to provide power to the
digital section.
Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This will occur in 4100
cycles of the real time clock after RESETZ goes high, at which time the MPU will begin executing its preboot and boot
sequences from address 00. See the security section for more description of preboot and boot.
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