71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
AUGUST 2007
71M651X
XIN
crystal
XOUT
Figure 9: Oscillator Circuit
The oscillator should be placed as close as possible to the IC, and vias should be avoided. An external resistor
across the crystal must not be added.
Real-Time Clock (RTC)
The RTC is driven directly by the crystal oscillator. In the absence of the 3.3V supply, the RTC is powered by the external
battery (VBAT pin). The RTC consists of a counter chain and output registers. The counter chain consists of seconds, minutes,
hours, day of week, day of month, month, and year. The RTC is capable of processing leap years. Each counter has its own
output register. Whenever the MPU reads the seconds register, all other output registers are automatically updated. Since the
RTC clock is not coherent to the MPU clock, the MPU must read the seconds register until two consecutive reads are the
same (requires either 2 or 3 reads). At this point, all RTC output registers will have the correct time. Regardless of the MPU
clock speed, RTC reads require one wait state.
The RTC interrupt must be enabled using the I/O RAM register EX_RTC (address 0x2002[1]). RTC time is set by writing to the
I/O RAM registers RTC_SEC, RTC_MIN, through RTC_YR. Each byte written to RTC must be delayed at least 3 CK32 cycles
from any previous byte written to RTC.
Two time correction bits, the I/O RAM registers RTC_DEC_SEC (0x201C[1]) and RTC_INC_SEC (0x201C[0]) are provided to
adjust the RTC time. A pulse on one of these bits causes the time to be decremented or incremented by an additional second
at the next update of the RTC_SEC register. Thus, if the crystal temperature coefficient is known, the MPU firmware can
integrate temperature and correct the RTC time as necessary as discussed in temperature compensation.
LCD Drivers
The 71M6511 contains 15 dedicated LCD segment pins, 5 LCD segment pins that rare shared with the SSI port and/or other
functions, and an additional 12 multi-purpose pins (LCD/DIO) that may be configured as LCD segment drivers (see I/O RAM
register LCD_NUM). Thus, the 71M6511/6511H is capable of driving between 80 to 128 pixels of LCD display with 25% duty
cycle. At seven segments per digit, the LCD can be designed for 11 to 18 digits for display. Since each pixel is addressed
individually, the LCD display can be a combination of alphanumeric digits and enunciator symbols. The information to be
displayed is written into the lower four bits of I/O RAM registers LCD_SEG0 through LCD_SEG37. Bit 0 corresponds to the
segment selected when COM0 pin is active while bit 1 is allocated to COM1.
The LCD driver circuitry is grouped into four common outputs (COM0 to COM3) and up to 32 segment outputs (see Table 56).
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