TSC80251G2D
Signal
Name
Alternate
Function
Type
Description
VSS
GND
GND
Circuit Ground
Connect this pin to ground.
VSS1
Secondary Ground 1
This ground is provided to reduce ground bounce and improve power supply bypassing.
Connection of this pin to ground is recommended. However, when using the TSC80251G2D
as a pin-for-pin replacement for a 8xC51 product, VSS1 can be unconnected without loss of
compatibility.
Not available on DIP package.
VSS2
GND
Secondary Ground 2
This ground is provided to reduce ground bounce and improve power supply bypassing.
Connection of this pin to ground is recommended. However, when using the TSC80251G2D
as a pin-for-pin replacement for a 8xC51 product, VSS2 can be unconnected without loss of
compatibility.
Not available on DIP package.
WAIT#
WCLK
I
Real-time Synchronous Wait States Input
P1.6
The real-time WAIT# input is enabled by setting RTWE bit in WCON (S:A7h). During bus
cycles, the external memory system can signal ‘system ready’ to the microcontroller in real
time by controlling the WAIT# input signal.
O
Wait Clock Output
P1.7
P3.6
The real-time WCLK output is enabled by setting RTWCE bit in WCON (S:A7h). When
enabled, the WCLK output produces a square wave signal with a period of one half the
oscillator frequency.
WR#
O
I
Write
Write signal output to external memory.
XTAL1
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external
oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal
timing.
XTAL2
O
Output of the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external
oscillator is used, leave XTAL2 unconnected.
Note:
1. The description of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the Non-Page mode chip configuration. If the chip is configured in Page mode
operation, port 0 carries the lower address bits (A7:0) while port 2 carries the upper address bits (A15:8) and the data (D7:0).
8
Rev. A - May 7, 1999
TEMIC [ TEMIC SEMICONDUCTORS ]
