TSC80251G2D
6.2 Data Memory
The TSC80251G2D derivatives implement 1 Kbyte of on-chip data RAM. Figure 6 shows the split of the internal
and external data memory spaces. This memory is mapped in the data space just over the 32 bytes of registers
area (see TSC80251 Programmers’ Guide). Hence, the part of the on-chip RAM located from 20h to FFh is bit
addressable. This on-chip RAM is not accessible through the program/code memory space.
For faster computation with the on-chip ROM/EPROM code of the TSC83251G2D/TSC87251G2D, its upper 16
Kbytes are also mapped in the upper part of the region 00: if the On-Chip Code Memory Map configuration bit
is cleared (EMAP# bit in UCONFIG1 byte, see Figure 8). However, if EA# is tied to a low level, the TSC80251G2D
derivative is running as a ROMless product and the code is actually fetched in the corresponding external memory
(i.e. the upper 16 Kbytes of the lower 32 Kbytes of the segment FF:). If EMAP# bit is set, the on-chip ROM is
not accessible through the region 00:.
All the accesses to the portion of the data space with no on-chip memory mapped onto are redirected to the external
memory.
Data External
Memory Space
On-chip ROM/EPROM
Code Memory
Data Segments
FF:FFFFh
32 Kbytes
32 Kbytes
FF:8000h
FF:7FFFh
16 Kbytes
16 Kbytes
EA#= 0
EA#= 1
FF:0000h
FE:FFFFh
64 Kbytes
FE:0000h
FD:FFFFh
EMAP#= 0
Reserved
02:0000h
01:FFFFh
64 Kbytes
01:0000h
00:FFFFh
RAM Data
16 Kbytes
EMAP#= 1
00:C000h
00:BFFFh
1 Kbyte
≈47 Kbytes
00:0420h
32 bytes reg.
Figure 6. Data Memory Mapping
6.3 Special Function Registers
The Special Function Registers (SFRs) of the TSC80251G2D derivatives fall into the categories detailed in Table 3
to Table 11.
SFRs are placed in a reserved on-chip memory region S: which is not represented in the data memory mapping
(Figure 6). The relative addresses within S: of these SFRs are provided together with their reset values in Table 12.
They are upward compatible with the SFRs of the standard 80C51 and the Intel’s 80C251Sx family. In this table,
the C251 core registers are identified by Note 1 and are described in the TSC80251 Programmer’s Guide. The
other SFRs are described in the TSC80251G1D Design Guide. All the SFRs are bit-addressable using the C251
instruction set.
10
Rev. A - May 7, 1999
TEMIC [ TEMIC SEMICONDUCTORS ]
