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TSC80251G2D-24CB 参数 Datasheet PDF下载

TSC80251G2D-24CB图片预览
型号: TSC80251G2D-24CB
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器,串行通信接口 [8/16-bit Microcontroller with Serial Communication Interfaces]
分类和应用: 微控制器外围集成电路异步传输模式ATM通信时钟
文件页数/大小: 63 页 / 813 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
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TSC80251G2D  
6. Address Spaces  
The TSC80251G2D derivatives implement four different address spaces:  
On-chip ROM program/code memory (not present in ROMless devices)  
On-chip RAM data memory  
Special Function Registers (SFRs)  
Configuration array  
6.1 Program/Code Memory  
The TSC83251G2D and TSC87251G2D implement 32 Kbytes of on-chip program/code memory. Figure 5 shows  
the split of the internal and external program/code memory spaces. If EA# is tied to a high level, the 32-Kbyte  
on-chip program memory is mapped in the lower part of segment FF: where the C251 core jumps after reset. The  
rest of the program/code memory space is mapped to the external memory. If EA# is tied to a low level, the  
internal program/code memory is not used and all the accesses are directed to the external memory.  
The TSC83251G2D products provide the internal program/code memory in a masked ROM memory while the  
TSC87251G2D products provide it in an EPROM memory. For the TSC80251G2D products, there is no internal  
program/code memory and EA# must be tied to a low level.  
Program/code  
External Memory Space  
Program/code  
Segments  
On-chip ROM/EPROM  
Code Memory  
FF:FFFFh  
32 Kbytes  
32 Kbytes  
FF:8000h  
FF:7FFFh  
EA#= 0  
EA#= 1  
32 Kbytes  
FF:0000h  
FE:FFFFh  
64 Kbytes  
FE:0000h  
FD:FFFFh  
Reserved  
02:0000h  
01:FFFFh  
01:0000h  
00:FFFFh  
128 Kbytes  
00:0000h  
Figure 5. Program/Code Memory Mapping  
Notes:  
Special care should be taken when the Program Counter (PC) increments:  
1. If the program executes exclusively from on-chip code memory (not from external memory), beware of executing code from the upper eight  
bytes of the on-chip ROM (FF:7FF8h-FF:7FFFh). Because of its pipeline capability, the TSC80251G2D derivative may attempt to prefetch  
code from external memory (at an address above FF:7FFFh) and thereby disrupt I/O Ports 0 and 2. Fetching code constants from these  
8 bytes does not affect Ports 0 and 2.  
2. When PC reaches the end of segment FF:, it loops to the reset address FF:0000h (for compatibility with the C51 Architecture). When PC  
increments beyond the end of segment FE:, it continues at the reset address FF:0000h (linearity). When PC increments beyond the end of  
segment 01:, it loops to the beginning of segment 00: (this prevents from its going into the reserved area).  
Rev. A - May 7, 1999  
9
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