TSC80251G2D
Symbol
Parameter
Min
Max
Unit
Master mode(3)
T
T
T
T
T
T
T
T
T
T
T
Clock Period
4
T
T
T
CHCH
CHCX
CLCX
OSC
Clock High Time
Clock Low Time
1.6
1.6
50
50
OSC
OSC
, T
Input Data Valid to Clock Edge
Input Data Hold after Clock Edge
Output Data Valid after Clock Edge
Output Data Hold Time after Clock Edge
Input Data Rise Time
ns
IVCL
CLIX
IVCH
CHIX
, T
ns
ns
ns
µs
µs
ns
ns
T
65
CLOV, CHOV
, T
0
CLOX
ILIH
CHOX
2
2
Input Data Fall Time
IHIL
Output Data Rise time
50
50
OLOH
Output Data Fall Time
OHOL
Notes:
1. Capacitive load on all pins= 200 pF in slave mode.
2. The value of this parameter depends on software.
3. Capacitive load on all pins= 100 pF in master mode.
Waveforms
(1)
SS#
(output)
T
CHCH
T
T
CLCH
SCK
(SSCPOL= 0)
(output)
T
T
CLCX
CHCX
CHCL
SCK
(SSCPOL= 1)
(output)
T
T
T
T
IVCH
IVCL
CHIX
CLIX
MISO
(input)
MSB IN
BIT 6
LSB IN
T
T
T
T
CLOV
CHOV
CLOX
CHOX
MOSI
(output)
Port Data
MSB OUT
BIT 6
LSB OUT
Port Data
Note:
1. SS# handled by software.
Figure 27. SPI Master Waveforms (SSCPHA= 0)
50
Rev. A - May 7, 1999
TEMIC [ TEMIC SEMICONDUCTORS ]
