TSC80251G2D
11.5 AC Characteristics - SSLC: I C Interface
2
Timings
2
Table 53. I C Interface AC Timing; V = 2.7 to 5.5 V, T = -40 to 85°C
DD
A
INPUT
OUTPUT
Symbol
Parameter
Min
Max Min
Max
(4)
(4)
(4)
(1)
THD; STA
TLOW
Start condition hold time
14·TCLCL
16·TCLCL
14·TCLCL
4.0 µs
4.7 µs
(1)
SCL low time
SCL high time
SCL rise time
SCL fall time
Data set-up time
(1)
THIGH
4.0 µs
(2)
TRC
1 µs
-
(3)
TFC
0.3 µs
0.3 µs
(4)
TSU; DAT1
TSU; DAT2
TSU; DAT3
THD; DAT
TSU; STA
TSU; STO
TBUF
250 ns
20·TCLCL - TRD
(1)
SDA set-up time (before repeated START condition)
SDA set-up time (before STOP condition)
Data hold time
250 ns
1 µs
(4)
250 ns
8·TCLCL
(4)
0 ns
8·TCLCL - TFC
(4)
(4)
(4)
(1)
Repeated START set-up time
STOP condition set-up time
Bus free time
14·TCLCL
14·TCLCL
14·TCLCL
4.7 µs
(1)
4.0 µs
(1)
4.7 µs
(2)
(3)
TRD
SDA rise time
1 µs
-
TFD
SDA fall time
0.3 µs
0.3 µs
Notes:
1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and
SCL= 400 pF.
4. TCLCL= T
OSC
= one oscillator clock period.
Waveforms
Repeated START condition
START or Repeated START condition
START condition
STOP condition
TSU;STA
TRD
0.7 V
DD
SDA
0.3 V
(INPUT/OUTPUT)
DD
TFD
TSU;STO
TBUF
TSU;DAT3
TRC
TFC
0.7 V
DD
SCL
0.3 V
(INPUT/OUTPUT)
DD
THD;STA
TLOW THIGH TSU;DAT1 THD;DAT
TSU;DAT2
2
Figure 26. I C Waveforms
48
Rev. A - May 7, 1999
TEMIC [ TEMIC SEMICONDUCTORS ]
