TSC80251G2D
ALE
WR#
(1)
T
LHLL
(1)
WLWH
T
T
WHLH
(1)
T
LHAX
T
QVWH
(1)
T
T
T
AVLL
LLAX
WHQX
P0
A7:0
D7:0
(1)
Data Out
T
AVWL1
(1)
T
T
AVWL2
WHAX
P2/A16/A17
A15:8/A16/A17
Note:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
Figure 18. External Bus Cycle: Data Write (Non-Page Mode)
Waveforms in Page Mode
ALE
(1)
T
LHLL
(1)
T
LLRL
(3)
PSEN#
(1)
RLDV
T
T
RLAZ
(1)
T
LHAX
T
RHDZ1
(1)
T
T
LLAX
AVLL
T
RHDX
P2
A15:8
D7:0
D7:0
Instruction In
(1)
Instruction In
T
AVRL
(1)
T
T
AXDX
AVDV1
(1)
(1)
AVDV3
T
T
AVDV2
T
RHAX
P0/A16/A17
A7:0/A16/A17
A7:0/A16/A17
(2)
(2)
Page Miss
Page Hit
Notes:
1. The value of this parameter depends on wait states. See Table 45 and Table 46.
2. A page hit (i.e., a code fetch to the same 256-byte “page” as the previous code fetch) requires one state (2·T
);
OSC
a page miss requires two states (4·T
).
OSC
3. During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
Figure 19. External Bus Cycle: Code Fetch (Page Mode)
Rev. A - May 7, 1999
43
TEMIC [ TEMIC SEMICONDUCTORS ]
