TSC80251G2D
Table 45. Bus Cycles AC Timings; V = 4.5 to 5.5 V, T = -40 to 85°C
DD
A
12 MHz
16 MHz
24 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
T
1/F
83
78
62
58
41
38
37
3
ns
OSC
OSC
(2)
T
ALE Pulse Width
ns
LHLL
AVLL
LLAX
(2)
T
T
Address Valid to ALE Low
78
58
ns
Address hold after ALE Low
RD#/PSEN# Pulse Width
19
11
ns
(1)
RLRH
(3)
T
162
165
22
121
124
14
78
81
6
ns
(3)
T
WR# Pulse Width
ns
WLWH
(1)
T
ALE Low to RD#/PSEN# Low
ALE High to Address Hold
ns
LLRL
(2)
T
99
70
40
ns
LHAX
(1)
(3)
T
RD#/PSEN# Low to Valid Data
Data Hold After RD#/PSEN# High
Address Hold After RD#/PSEN# High
RD#/PSEN# Low to Address Float
Instruction Float After RD#/PSEN# High
Data Float After RD#/PSEN# High
RD#/PSEN# high to ALE High (Instruction)
RD#/PSEN# high to ALE High (Data)
WR# High to ALE High
146
104
61
ns
RLDV
RHDX
RHAX
(1)
(1)
T
T
T
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
(1)
0
0
0
RLAZ
T
45
40
30
RHDZ1
RHDZ2
RHLH1
RHLH2
T
T
T
215
165
115
49
43
31
215
215
169
169
115
115
T
ns
WHLH
(2)(3)
T
T
T
Address (P0) Valid to Valid Data In
Address (P2) Valid to Valid Data In
Address (P0) Valid to Valid Instruction In
Data Hold after Address Hold
Address Valid to RD# Low
250
306
150
175
223
109
105
140
68
ns
AVDV1
AVDV2
AVDV3
(2)(3)
ns
(3)
ns
T
0
0
0
ns
AXDX
(1)
(2)
T
100
100
158
90
70
40
40
74
32
72
84
ns
AVRL
(2)
T
Address (P0) Valid to WR# Low
Address (P2) Valid to WR# Low
Data Hold after WR# High
70
ns
ns
AVWL1
AVWL2
(2)
T
115
69
T
ns
WHQX
QVWH
WHAX
(3)
T
Data Valid to WR# High
133
167
102
125
ns
T
WR# High to Address Hold
ns
Notes:
1. Specification for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2·T
OSC.
3. If wait states are added by extending RD#/PSEN#/WR#, add 2N·T
(N= 1..3).
OSC
40
Rev. A - May 7, 1999
TEMIC [ TEMIC SEMICONDUCTORS ]
