TSC80251G2D
11. AC Characteristics - Commercial & Industrial
11.1 AC Characteristics - External Bus Cycles
Definition of symbols
Table 44. External Bus Cycles Timing Symbol Definitions
Signals
Conditions
A
D
L
Address
H
L
High
Data In
ALE
Low
V
X
Z
Valid
Q
R
W
Data Out
RD#/PSEN#
WR#
No Longer Valid
Floating
Timings
Test conditions: capacitive load on all pins= 50 pF.
Table 45 and Table 46 list the AC timing parameters for the TSC80251G2D derivatives with no wait states. External
wait states can be added by extending PSEN#/RD#/WR# and or by extending ALE. In these tables, Note 2 marks
parameters affected by one ALE wait state, and Note 3 marks parameters affected by PSEN#/RD#/WR# wait states.
Figure 16 to Figure 21 show the bus cycles with the timing parameters.
Rev. A - May 7, 1999
39
TEMIC [ TEMIC SEMICONDUCTORS ]
