欢迎访问ic37.com |
会员登录 免费注册
发布采购

TSC80251G2D-24CB 参数 Datasheet PDF下载

TSC80251G2D-24CB图片预览
型号: TSC80251G2D-24CB
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器,串行通信接口 [8/16-bit Microcontroller with Serial Communication Interfaces]
分类和应用: 微控制器外围集成电路异步传输模式ATM通信时钟
文件页数/大小: 63 页 / 813 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
 浏览型号TSC80251G2D-24CB的Datasheet PDF文件第27页浏览型号TSC80251G2D-24CB的Datasheet PDF文件第28页浏览型号TSC80251G2D-24CB的Datasheet PDF文件第29页浏览型号TSC80251G2D-24CB的Datasheet PDF文件第30页浏览型号TSC80251G2D-24CB的Datasheet PDF文件第32页浏览型号TSC80251G2D-24CB的Datasheet PDF文件第33页浏览型号TSC80251G2D-24CB的Datasheet PDF文件第34页浏览型号TSC80251G2D-24CB的Datasheet PDF文件第35页  
TSC80251G2D  
VDD  
VDD  
RST  
VDD  
V
EA#/VPP  
ALE/PROG#  
PSEN#  
PP  
100 µs pulses  
TSC87251G2D  
Mode  
A[7:0]  
A[14:8]  
Data  
P0[7:0]  
P3[7:0]  
P1[7:0]  
P2[7:0]  
4 to 12 MHz  
XTAL1  
VSS/VSS1/VSS2  
Figure 9. Setup for Programming  
Table 38. Programming Modes  
ROM Area(1)  
RST  
EA#/VPP PSEN# ALE/PROG#(2)  
P0  
P2  
P1(MSB) P3(LSB)  
16-bit Address  
0000h-7FFFh (32 Kbytes)  
On-chip Code Memory  
1
V
0
0
1 Pulse  
1 Pulse  
68h  
Data  
PP  
PP  
CONFIG0: FFF8h  
CONFIG1: FFF9h  
Configuration Bytes  
Lock Bits  
1
V
69h  
Data  
LB0: 0001h  
LB1: 0002h  
LB2: 0003h  
1
1
V
V
0
0
1 Pulse  
1 Pulse  
6Bh  
6Ch  
X
PP  
Encryption Array  
Data  
0000h-007Fh  
PP  
Notes:  
1. Signature Bytes are not user-programmable.  
2. The ALE/PROG# pulse waveform is shown in Figure 31 page 54.  
8.5 Verify Algorithm  
Figure 10 shows the hardware setup needed to verify the TSC87251G2D EPROM/OTPROM or TSC83251G2D  
ROM areas:  
The chip has to be put under reset and maintained in this state until the completion of the verifying sequence.  
PSEN# and the other control signals (ALE and Port 0) have to be set to a high level.  
Then PSEN# has to be to forced to a low level after two clock cycles or more and it has to be maintained in  
this state until the completion of the verifying sequence (see below).  
The voltage on the EA# pin must be set to V  
and ALE must be set to a high level.  
DD  
The Verifying Mode is selected according to the code applied on Port 0. It has to be applied until the completion  
of this verifying operation.  
The verifying address is applied on Ports 1 and 3 which are respectively the MSB and the LSB of the address.  
Then device is driving the data on Port 2.  
It is possible to alternate programming and verification operation (see Paragraph 8.4). Please make sure the  
voltage on the EA# pin has actually been lowered to V  
before performing the verifying operation.  
DD  
PSEN# and the other control signals have to be released to complete a sequence of verifying operations or a  
sequence of programming and verifying operations.  
31  
Rev. A - May 7, 1999  
 复制成功!