TSC80251G2D
Table 39. Verifying Modes
ROM Area(1)
RST
EA#/VPP PSEN# ALE/PROG#
P0
P2
P1(MSB) P3(LSB)
16-bit Address
0000h-7FFFh (32 Kbytes)
On-chip code memory
1
1
1
0
0
1
1
28h
Data
CONFIG0: FFF8h
CONFIG1: FFF9h
Configuration Bytes
1
29h
Data
Lock Bits
Signature Bytes
Note:
1
1
1
1
0
0
1
1
2Bh
29h
Data
Data
0000h
0030h, 0031h, 0060h, 0061h
1. To preserve the secrecy of on-chip code memory when encrypted, the Encryption Array can not be verified.
VDD
VDD
RST
VDD
EA#/VPP
ALE/PROG#
PSEN#
TSC8x251G2D
Mode
A[7:0]
P0[7:0]
P3[7:0]
P1[7:0]
P2[7:0]
Data
XTAL1
4 to 12 MHz
A[14:8]
VSS/VSS1/VSS2
Figure 10. Setup for Verifying
Rev. A - May 7, 1999
32