TSC87251G1A
Table 1. TSC87251G1A Pin Assignment
DIP
PLCC
Name
DIP
PLCC
Name
1
2
VSS1
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VSS2
1
2
P1.0/T2
21
22
23
24
25
26
27
28
29
30
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN#
3
P1.1/T2EX
P1.2/ECI
3
4
4
5
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2/MISO
5
6
6
7
7
8
P1.6/CEX3/SCL/SCK
P1.7/A17/CEX4/SDA/MOSI
RST
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
10
P3.0/RXD
NC
ALE/PROG#
NC
11
12
13
14
15
16
17
18
19
20
P3.1/TXD
P3.2/INT0#
P3.3/INT1#
P3.4/T0
31
32
33
34
35
36
37
38
39
40
EA#/VPP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VDD
P3.5/T1
P3.6/WR#
P3.7/A16/RD#
XTAL2
XTAL1
VSS
5.2. Signals
Table 2. TSC87251G1A Signal Descriptions
Description
Signal
Name
Alternate
Function
Type
th
A17
O
18 Address Bit
P1.7
Output to memory as 18th external address bit (A17) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13).
th
A16
O
17 Address Bit
Output to memory as 17th external address bit (A16) in extended bus applications, depending
on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13).
Address Lines
P3.7
(1)
A15:8
O
I/O
O
P2.7:0
P0.7:0
Upper address lines for the external bus.
(1)
AD7:0
Address/Data Lines
Multiplexed lower address lines and data for the external memory.
ALE
Address Latch Enable
ALE signals the start of an external bus cycle and indicates that valid address information are
available onlines A16/A17 and A7:0. An external latch can use ALE to demultiplex the address
from address/databus.
CEX4:0
EA#
O
I
PCA Input/Output pins
P1.7:3
CEXx are input signals for the PCA capture mode and output signals for the PCA compare and
PWM modes.
External Access Enable
EA# directs program memory accesses to on–chip or off–chip code memory.
For EA#= 0, all program memory accesses are off-chip.
For EA#= 1, an access is on-chip EPROM/OTPROM if the address is within the range of the on–
chip EPROM/OTPROM; otherwise the access is off-chip. The value of EA# is latched at reset.
5
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
