TSC87251G1A
6. Address Spaces
The TSC87251G1A implements four different address spaces:
D On–chip EPROM/OTPROM program/code memory
D On–chip RAM data memory
D Special Function Registers (SFRs)
D Configuration array
6.1. Program/Code Memory
The TSC87251G1A implements 16 Kbytes of on–chip EPROM/OTPROM for program/code memory. Figure 4 shows
the split of the internal and external program/code memory spaces. If EA# is tied to a high level, the 16–Kbyte on–chip
program/code memory is mapped in the lower part of segment FF: where the C251 core jumps after reset. The rest of
the program/code memory space is mapped to the external memory. If EA# is tied to a low level, the internal
program/code memory is not used and all the accesses are directed to the external memory.
Program/code
External Memory Space
Program/code
Segments
On–chip Memory
EPROM/OTPROM Code
FF:FFFFh
48 Kbytes
FF:4000h
FF:3FFFh
FF:0000h
16 Kbytes
64 Kbytes
EA#= 0
EA#= 1
16 Kbytes
FE:FFFFh
FE:0000h
FD:FFFFh
Reserved
02:0000h
01:FFFFh
01:0000h
00:FFFFh
128 Kbytes
00:0000h
Figure 4. Program/Code Memory Mapping
Notes:
Special care should be taken when the Program Counter (PC) increments:
– If the program executes exclusively from on–chip code memory (not from external memory), beware of executing code from the upper eight bytes of
the on–chip EPROM (FF:3FF8h–FF:3FFFFh). Because of its pipeline capability, the TSC87251G1A may attempt to prefetch code from external
memory (at an address above FF:3FFFFh) and thereby disrupt I/O Ports 0 and 2. Fetching code constants from these 8 bytes does not affect Ports 0
and 2.
– When PC reaches the end of segment FF:, it loops to the reset address FF:0000h (for compatibility with the C51 Architecture). When PC increments
beyond the end of segment FE:, it continues at the reset address FF:0000h (linearity). When PC increments beyond the end of segment 01:, it loops to
the beginning of segment 00: (this prevents from its going into the reserved area).
8
Rev. A – September 21, 1998
TEMIC [ TEMIC SEMICONDUCTORS ]
