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TSC87251G1A-16CA 参数 Datasheet PDF下载

TSC87251G1A-16CA图片预览
型号: TSC87251G1A-16CA
PDF下载: 下载PDF文件 查看货源
内容描述: 扩展8位微控制器的串行通信 [Extended 8?bit Microcontroller with Serial Communication]
分类和应用: 微控制器光电二极管通信可编程只读存储器
文件页数/大小: 52 页 / 341 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
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TSC87251G1A  
3. Features  
D Pin–Out and software compatibility with standard  
D Secured 14–bit Hardware Watchdog Timer  
D Power Monitoring and Management  
80C51 products and 80C51FA/FB/RA/RB  
D Plug–in replacement of Intel’s 80C251Sx  
G
G
G
G
G
Power–Fail reset  
R
D C251 core: Intel’s MCS 251 step A compliance  
Power–On reset (integrated on the chip)  
Power–Off flag (cold and warm resets)  
Software programmable system clock  
Idle and Power–Down modes  
G
G
G
G
G
125 ns Instruction cycle time at 16 MHz  
40–byte Register File  
Registers Accessible as Bytes, Words or Dwords  
Six–stage instruction Pipeline  
D Keyboard interrupt interface on Port 1  
16–bit Internal Code Fetch  
D ONCE mode and full speed Real–Time In–Circuit  
D Enriched C51 Instruction Set  
Emulation support (Third Party Vendors)  
G
G
G
16–bit and 32–bit ALU  
D Speed ranges:  
Compare and Conditional Jump Instructions  
Expanded Set of Move Instructions  
G
0 to 16 MHz  
D Supply ranges:  
D Linear Addressing  
G
5 V ±10 %  
D 1 Kbyte of on–chip RAM  
D Temperature ranges:  
D External memory space (Code/Data) programmable  
G
G
G
Commercial (0°C to +70°C)  
from 64 Kbytes to 256 Kbytes  
Industrial (–40°C to +85°C)  
D TSC87251G1A: 16 Kbytes of on–chip EPROM/  
OTPROM (production with TSC83251G1D:  
on–chip masked ROM version)  
Option: extended range (–55°C to +125°C)  
D Packages:  
D SINGLE–PULSE Programming Algorithm  
G
G
G
PDIL 40, PLCC 44  
D Four 8–bit parallel I/O Ports (Ports 0, 1, 2 and 3 of the  
UV–Window CQPJ 44  
standard 80C51)  
Options: known good dice and ceramic packages  
D Serial I/O Port: full duplex UART (80C51  
compatible) with independent Baud Rate Generator  
D SSLC: Synchronous Serial Link Controller  
2
G
G
I C master only protocol  
µWire and SPI master only protocol  
D Three 16–bit Timers/Counters (Timers 0, 1 and 2 of  
the standard 80C51)  
D EWC: Event and Waveform Controller  
G
G
Compatible with Intel’s Programmable Counter  
Array (PCA)  
Common 16–bit Timer/Counter reference with  
four possible clock sources (Fosc/4, Fosc/12,  
Timer 1 and external input)  
G
G
Five modules with four programmable modes:  
16–bit software Timer/Counter  
16–bit Timer/Counter Capture Input and  
software pulse measurement  
High–speed output and 16–bit software Pulse  
Width Modulation (PWM)  
8–bit hardware PWM without overhead  
16–bit Watchdog Timer/Counter capability  
2
Rev. A September 21, 1998