TS80C52X2
Table 4. CKCON Register
CKCON - Clock Control Register (8Fh)
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
X2
Bit
Number
Bit
Mnemonic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
7
6
5
4
3
2
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
-
-
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, F
=FXTAL/2).
0
X2
OSC
Set to select 6 clock periods per machine cycle (X2 mode, F
=F
).
OSC XTAL
Reset Value = XXXX XXX0b
Not bit addressable
Rev. B - Jan. 25, 1999
9
Preliminary
TEMIC [ TEMIC SEMICONDUCTORS ]
