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TS80C32X2-LCBR 参数 Datasheet PDF下载

TS80C32X2-LCBR图片预览
型号: TS80C32X2-LCBR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS微控制器0-60兆赫 [8-bit CMOS Microcontroller 0-60 MHz]
分类和应用: 微控制器和处理器外围集成电路异步传输模式ATM时钟
文件页数/大小: 54 页 / 584 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
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TS80C52X2  
6.3 Timer 2  
The timer 2 in the TS80C52X2 is compatible with the timer 2 in the 80C52.  
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in  
cascade. It is controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation  
is similar to Timer 0 and Timer 1. C/T2 selects F  
/12 (timer operation) or external pin T2 (counter operation)  
OSC  
as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.  
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the  
combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the TEMIC 8-bit Microcontroller Hardware  
description.  
Refer to the TEMIC 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate  
Generator Modes.  
In TS80C52X2 Timer 2 includes the following enhancements:  
Auto-reload mode with up or down counter  
Programmable clock-output  
6.3.1 Auto-Reload Mode  
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit  
in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the TEMIC 8-bit Microcontroller Hardware description).  
If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 4. In this mode the T2EX pin  
controls the direction of count.  
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates  
an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded  
into the timer registers TH2 and TL2.  
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and  
TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh  
into the timer registers.  
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2  
does not generate any interrupt. This bit can be used to provide 17-bit resolution.  
Rev. B - Jan. 25, 1999  
13  
Preliminary  
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