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TS80C32X2-LCBR 参数 Datasheet PDF下载

TS80C32X2-LCBR图片预览
型号: TS80C32X2-LCBR
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS微控制器0-60兆赫 [8-bit CMOS Microcontroller 0-60 MHz]
分类和应用: 微控制器和处理器外围集成电路异步传输模式ATM时钟
文件页数/大小: 54 页 / 584 K
品牌: TEMIC [ TEMIC SEMICONDUCTORS ]
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TS80C52X2  
ASSEMBLY LANGUAGE  
; Block move using dual data pointers  
; Destroys DPTR0, DPTR1, A and PSW  
; note: DPS exits opposite of entry state  
; unless an extra INC AUXR1 is added  
;
00A2  
;
AUXR1 EQU 0A2H  
0000 909000MOV DPTR,#SOURCE  
0003 05A2 INC AUXR1  
0005 90A000 MOV DPTR,#DEST  
; address of SOURCE  
; switch data pointers  
; address of DEST  
0008  
LOOP:  
0008 05A2 INC AUXR1  
; switch data pointers  
000A E0  
000B A3  
000C 05A2 INC AUXR1  
MOVX A,@DPTR  
INC DPTR  
; get a byte from SOURCE  
; increment SOURCE address  
; switch data pointers  
000E F0  
000F A3  
0010 70F6 JNZ LOOP  
0012 05A2 INC AUXR1  
MOVX @DPTR,A  
INC DPTR  
; write the byte to DEST  
; increment DEST address  
; check for 0 terminator  
; (optional) restore DPS  
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However,  
note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it.  
In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence  
matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1'  
on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the  
opposite state.  
12  
Rev. B - Jan. 25, 1999  
Preliminary  
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