SUP/SUB75N06-08
Specifications (TJ = 25_C Unless Otherwise Noted)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Static
DrainĆSource Breakdown Voltage
Gate Threshold Voltage
V
V
= 0 V, I = 250 mA
60
(BR)DSS
GS
D
V
V
V
= V , I = 250 mA
2.0
3.0
4.0
"100
1
GS(th)
DS
GS
D
Gate-Body Leakage
I
V
= 0 V, V = "20 V
nA
GSS
DS
GS
V
= 60 V, V = 0 V
GS
DS
Zero Gate Voltage Drain Current
I
V
V
= 60 V V = 0 V, T = 125_C
50
mA
A
DSS
DS
,
GS
J
= 60 V, V = 0 V, T = 175_C
150
DS
GS
J
b
On-State Drain Current
I
V
= 5 V, V = 10 V
120
30
D(on)
DS
GS
V
= 10 V, I = 30 A
0.007
0.008
0.012
0.016
GS
D
b
Drain-Source On-State Resistance
r
W
S
V
= 10 V, I = 30 A, T = 125_C
DS(on)
GS
GS
D
J
V
= 10 V, I = 30 A, T = 175_C
D
J
b
Forward Transconductance
g
V
= 15 V, I = 30 A
DS D
fs
Dynamica
Input Capacitance
C
4800
910
270
85
iss
Output Capacitance
C
oss
V
= 0 V, V = 25 V, f = 1 MHz
pF
GS
DS
Reverse Transfer Capacitance
C
rss
c
Total Gate Charge
Q
120
g
c
Gate-Source Charge
Q
V
= 30 V V = 10 V, I = 75 A
28
nC
gs
gd
DS
,
GS
D
c
Gate-Drain Charge
Q
26
c
Turn-On Delay Time
t
20
40
200
120
60
d(on)
c
Rise Time
t
r
95
V
= 30 V, R = 0.47 W
L
= 10 V, R = 2.5 W
GEN G
DD
ns
I
D
^ 75 A, V
c
Turn-Off Delay Time
t
65
d(off)
c
Fall Time
t
f
20
SourceĆDrain Diode Ratings and CharacteriCstics= _(TC25)a
Continuous Current
I
75
240
1.3
120
8
S
A
Pulsed Current
I
SM
b
Forward Voltage
V
t
I
F
= 75 A , V = 0 V
1.0
67
6
V
ns
A
SD
GS
Reverse Recovery Time
rr
Peak Reverse Recovery Current
Reverse Recovery Charge
I
I = 75 A, di/dt = 100 A/ms
F
RM(REC)
Q
0.2
0.48
mC
rr
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test: pulse width v 300 msec, duty cycle v 2%.
c. Independent of operating temperature.
2
Siliconix
S-47969—Rev. D, 08-Jul-96
TEMIC [ TEMIC SEMICONDUCTORS ]
