ICM-20690
4 APPLICATIONS INFORMATION
4.1 PIN OUT DIAGRAM AND SIGNAL DESCRIPTION
Pin Number
Pin Name
Pin Description
Application Processor (AP) Interface: AP I2C slave address LSB (AP_AD0); AP
SPI serial data output (AP_SDO)
1
AP_AD0 / AP_SDO
2
3
OIS_SDIO / AUX_DA
OIS_SCLK / AUX_CL
INT1
OIS SPI serial data IO (OIS_SDIO); I2C master serial data (AUX_DA)
OIS SPI serial clock (OIS_SCLK); I2C master serial clock (AUX_CL)
Interrupt digital output (totem pole or open-drain)
Digital I/O supply voltage
4
5
VDDIO
6
GND
Power supply ground
7
RESV
Reserved, connect to ground
8
VDD
Power supply voltage
9
INT2
Interrupt digital output (totem pole or open-drain)
Frame synchronization digital input; OIS SPI chip select (OIS_CS)
Regulator filter capacitor connection
10
11
12
13
14
FSYNC / OIS_CS
REGOUT
AP_CS
AP SPI Chip select (SPI mode only)
AP_SCL / AP_SCLK
AP_SDA / AP_SDI
AP I2C serial clock (AP_SCL); AP SPI serial clock (AP_SCLK)
AP I2C serial data (AP_SDA); AP SPI serial data input (AP_SDI)
Table 10. Signal Descriptions
Note: Power up with AP_SCL / AP_SCLK and AP_CS pins held low is not a supported use case. In case this power up approach is used, software
reset is required using the PWR_MGMT_1 register, prior to initialization.
AP_AD0 / AP_SDO
1
2
3
4
11
10
9
REGOUT
FSYNC / OIS_CS
INT2
+Z
OIS_SDIO / AUX_DA
OIS_SCLK / AUX_CL
INT1
I
C
M
ICM-20690
-
2
0
6
9
0
8
VDD
+Y
+X
Orientation of Axes of and Polarity of Rotation
LGA Package (Top view)
Figure 4. Pin Out Diagram for ICM-20690 2.5x3.0x0.91 mm LGA
Page 19 of 76
Document Number: DS-000178
Revision: 1.0
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