ICM-20690
3.6 SPI TIMING CHARACTERIZATION – 3-WIRE SPI MODE
The following section is applicable to 3-wire SPI mode for the Auxiliary Interface.
Typical Operating Circuit of section 4.2, VDD = 1.8 V, VDDIO = 1.8 V, TA=25°C, unless otherwise noted.
NOTES
PARAMETERS
CONDITIONS
MIN
TYP
MAX
UNITS
SPI TIMING
fSPC, SCLK Clock Frequency
tLOW, SCLK Low Period
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
1
1
1
1
1
1
1
2
2
30
30
tHIGH, SCLK High Period
tSU.CS, CS Setup Time
14.5
9
tHD.CS, CS Hold Time
tSU.SDIO, SDOI Input Setup Time
tHD.SDIO, SDIO Input Hold Time
tVD.SDIO, SDIO Output Valid Time
tHD.SDIO, SDIO Output Hold Time
tDIS.SDIO, SDIO Output Disable Time
tFall, SCLK Fall Time
3.5
8.5
Cload = 20 pF
Cload = 20 pF
21
19
41
8
tRise, SCLK Rise Time
8
Table 8. SPI Timing Characteristics (20-MHz Operation)
Notes:
1. Based on characterization of 5 parts over temperature and voltage as mounted on evaluation board or in sockets
2. Based on other parameter values
CS
70%
30%
tFall
tRise
tHD;CS
tSU;CS
70%
tHIGH
1/fCLK
SCLK
30%
tSU;SDIO
tHD;SDIO
tLOW
70%
30%
I
LSB IN
MSB IN
tDIS;SDIO
tVD;SDIO
tHD;SDIO
70%
30%
O
MSB OUT
LSB OUT
Figure 3. 3-Wire SPI Bus Timing Diagram
Page 17 of 76
Document Number: DS-000178
Revision: 1.0