ICM-20602
Burst Write Sequence
Master
Slave
S
AD+W
RA
DATA
DATA
P
ACK
ACK
ACK
ACK
To read the internal ICM-20602 registers, the master sends a start condition, followed by the I2C address and a write bit, and then
the register address that is going to be read. Upon receiving the ACK signal from the ICM-20602, the master transmits a start signal
followed by the slave address and read bit. As a result, the ICM-20602 sends an ACK signal and the data. The communication ends
with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high
at the 9th clock cycle. The following figures show single and two-byte read sequences.
Single-Byte Read Sequence
Master
Slave
S
AD+W
ACK
RA
S
AD+R
NACK
P
ACK
RA
ACK
ACK
DATA
ACK
Burst Read Sequence
Master
Slave
S
AD+W
S
AD+R
NACK
P
ACK
ACK DATA
DATA
6.4 I2C TERMS
Signal
Description
S
AD
Start Condition: SDA goes from high to low while SCL is high
Slave I2C address
W
Write bit (0)
R
Read bit (1)
ACK
NACK
RA
Acknowledge: SDA line is low while the SCL line is high at the 9th clock cycle
Not-Acknowledge: SDA line stays high at the 9th clock cycle
ICM-20602 internal register address
DATA
P
Transmit or received data
Stop condition: SDA going from low to high while SCL is high
Table 14. I2C Terms
6.5 SPI INTERFACE
SPI is a 4-wire synchronous serial interface that uses two control lines and two data lines. The ICM-20602 always operates as a Slave
device during standard Master-Slave SPI operation.
With respect to the Master, the Serial Clock output (SPC), the Serial Data Output (SDO) and the Serial Data Input (SDI) are shared
among the Slave devices. Each SPI slave device requires its own Chip Select (CS) line from the master.
CS goes low (active) at the start of transmission and goes back high (inactive) at the end. Only one CS line is active at a time, ensuring
that only one slave is selected at any given time. The CS lines of the non-selected slave devices are held high, causing their SDO lines
to remain in a high-impedance (high-z) state so that they do not interfere with any active devices.
SPI Operational Features
1. Data is delivered MSB first and LSB last
2. Data is latched on the rising edge of SPC
3. Data should be transitioned on the falling edge of SPC
4. The maximum frequency of SPC is 10MHz
5. SPI read and write operations are completed in 16 or more clock cycles (two or more bytes). The first byte contains the
SPI Address, and the following byte(s) contain(s) the SPI data. The first bit of the first byte contains the Read/Write bit
and indicates the Read (1) or Write (0) operation. The following 7 bits contain the Register Address. In cases of multiple-
byte Read/Writes, data is two or more bytes:
SPI Address format
MSB
LSB
R/W A6 A5 A4 A3 A2 A1 A0
Document Number: DS-000176
Revision: 1.0
Page 26 of 57
Revision Date: 10/03/2016
TDK [ TDK ELECTRONICS ]
