ICM-20602
6 DIGITAL INTERFACE
6.1 I2C AND SPI SERIAL INTERFACES
The internal registers and memory of the ICM-20602 can be accessed using either I2C at 400 kHz or SPI at 10MHz. SPI operates in
four-wire mode.
Pin Number
Pin Name
SCL / SPC
SDA / SDI
SA0 / SDO
CS
Pin Description
2
3
4
5
I2C serial clock (SCL); SPI serial clock (SPC)
I2C serial data (SDA); SPI serial data input (SDI)
I2C Slave Address LSB (SA0); SPI serial data output (SDO)
Chip select (0 = SPI mode)
Table 13. Serial Interface
Note: To prevent switching into I2C mode when using SPI, the I2C interface should be disabled by setting the I2C_IF_DIS configuration bit at I2C_IF. Setting this bit
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regarding the I2C_IF_DIS bit at I2C_IF register, please refer to sections 10 and 11 of this document.
6.2 I2C INTERFACE
I2C is a two-wire interface comprised of the signals serial data (SDA) and serial clock (SCL). In general, the lines are open-drain and bi-
directional. In a generalized I2C interface implementation, attached devices can be a master or a slave. The master device puts the
slave address on the bus, and the slave device with the matching address acknowledges the master.
The ICM-20602 always operates as a slave device when communicating to the system processor, which thus acts as the master. SDA
and SCL lines typically need pull-up resistors to VDD. The maximum bus speed is 400 kHz.
The slave address of the ICM-20602 is b110100X which is 7 bits long. The LSB bit of the 7 bit address is determined by the logic level
on pin SA0. This allows two ICM-20602s to be connected to the same I2C bus. When used in this configuration, the address of one of
the devices should be b1101000 (pin SA0 is logic low) and the address of the other should be b1101001 (pin SA0 is logic high).
6.3 I2C COMMUNICATIONS PROTOCOL
START (S) and STOP (P) Conditions
Communication on the I2C bus starts when the master puts the START condition (S) on the bus, which is defined as a HIGH-to-LOW
transition of the SDA line while SCL line is HIGH (see figure below). The bus is considered to be busy until the master puts a STOP
condition (P) on the bus, which is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH (see figure below).
Additionally, the bus remains busy if a repeated START (Sr) is generated instead of a STOP condition.
SDA
SCL
S
P
START condition
STOP condition
Figure 8. START and STOP Conditions
Data Format / Acknowledge
I2C data bytes are defined to be 8-bits long. There is no restriction to the number of bytes transmitted per data transfer. Each byte
transferred must be followed by an acknowledge (ACK) signal. The clock for the acknowledge signal is generated by the master,
while the receiver generates the actual acknowledge signal by pulling down SDA and holding it low during the HIGH portion of the
acknowledge clock pulse.
If a slave is busy and cannot transmit or receive another byte of data until some other task has been performed, it can hold SCL
LOW, thus forcing the master into a wait state. Normal data transfer resumes when the slave is ready, and releases the clock line
(refer to the following figure).
Document Number: DS-000176
Revision: 1.0
Page 24 of 57
Revision Date: 10/03/2016
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