78P2342JAT
2-port E3/DS3/STS-1 LIU
with Jitter Attenuator
The outputs of the data comparators are connected
to the clock recovery circuits. The clock recovery
system employs a digital PLL, which uses a line-rate
reference clock frequency applied to the CKREF pin.
The jitter tolerance of 78P2342 meets the
requirements of ITU-T G.823 for E3 rates; the
requirements of ITU-T G.824, GR-499 (Cat I and II)
for DS3 rates; and the requirements of GR-253 for
STS1 rates.
FUNCTIONAL DESCRIPTION
The 78P2342JAT contains all the necessary
transmit and receive circuitry for connection
between E3, DS3, or STS-1 line interfaces and
digital Framer/Mapper ICs.
OPERATING RATE
The Master Control Register (MSCR) determines
which mode the device operates in according to the
table below. The MSL0 pin is also provided for
mode selection in applications without a serial
control interface. Upon power-up or reset, the state
of the MSL0 pin is sensed and mapped into the DS3
and E3 register bits representing the appropriate
mode of operation. After power-up/reset, the state of
the MSL0 pin is ignored.
Without the Jitter Attenuator, the jitter transfer
function meets the requirements of GR-499 for
Category II DS3 interfaces.
When the Jitter Attenuator is enabled, the
78P2342JAT meets the requirements of GR-499
and GR-253 for all categories of DS3/STS1
equipment and the ETSI TBR-24 requirements for
E3 rates.
standards,
To check conformance with other
Standard
MSL0 pin
DS3 bit
E3 bit
please
refer
to
the
JITTER
E3
L
H
Z
Z
0
1
0
1
1
0
0
1
ATTENUATOR TRANSFER FUNCTION section for
more detailed info.
DS3
STS-1
STS-1
RECEIVER MONITOR MODE
When in monitor mode, 20dB of flat gain is applied
to the incoming signal before it is fed to the receive
equalizer. This mode is controlled by the MON bit in
the Mode Control Register.
RECEIVER OPERATION
The receiver input is either transformer-coupled or
capacitor-coupled to the line signal. In applications
where the highest performance and isolation are
required, a 1:1 transformer is used in the receive
path. In applications where isolation is provided
elsewhere in the circuit, capacitor coupling can be
used. The receiver input should be line terminated
externally with a termination resistor.
The AMI signal first enters an AGC, which has a
selectable gain range setting. In normal operation,
the AGC can compensate for signals with up to 6dB
of flat loss. When Receiver Monitor Mode is
enabled, the AGC can compensate for a DSX3
monitor signal with 16 to 20 dB of flat loss. The
signal then enters a high performance adaptive
equalizer. The equalizer is designed to overcome
inter-symbol interference caused by long cable
lengths. Because the equalizer is adaptive, the
circuit will work with all square-shaped signals such
as DS3-high or 34.368 Mbit/s E3. The variable gain
differential amplifier automatically controls the gain
to maintain
a
constant voltage level output
regardless of the input voltage level.
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TDK [ TDK ELECTRONICS ]
