CC2430
Peripherals : Flash Controller
Setup DMA channel:
SRCADDR=<XDATA location>
DESTADDRR=FWDATA
VLEN=0
LEN=<block size>
WORDSIZE=byte
TMODE=single mode
TRIG=FLASH
SRCINC=yes
DESTINC=no
IRQMASK=yes
M8=0
PRIORITY=high
Setup flash address
Arm DMA Channel
Start flash write
Figure 15: Flash write using DMA
13.3.2.2
CPU Flash Write
The CPU can also write directly to the flash
when executing program code from RAM
using Unified CODE memory space. The CPU
writes data to the Flash Write Data register,
FWDATA. The flash memory is written each
time four bytes have been written to FWDATA,
and FCTL.WRITE bit set to 1. The CPU can
poll the FCTL.SWBSY status to determine
when the flash is ready for four more bytes to
be written to FWDATA. Note that all flash writes
needs to be four bytes aligned. Also note that
there exist a timeout periode for writing to one
flash word, thus writing all four bytes to the
FWDATA register has to end within 40 µs after
FCTL.SWBSY went low in repeated writes, or
after FCTL.WRITE set for first time write. The
FCTL.BUSY=0 flag will indicate if the time out
happened or not. If FCTL.BUSY= 0 the write
ended and one have to start over again by
enabling the FCTL.WRITE bit. The address is
set for word to write to, but FWDATA has to be
updated again with the 4 bytes that casuse the
time out to happen.
Performing CPU flash write
The steps required to start a CPU flash write
operation are shown in Figure 16 on page 75.
Note that code must be run from RAM in
unified CODE memory space.
CC2430 Data Sheet (rev. 2.1) SWRS036F
Page 74 of 211
TAOS [ TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS ]
