SyncMOS Technologies International. Inc.
SM79108
SPFS[1:0]: These two bits is 2’s power parameter to form a frequency divider for input clock.
SPFS1
SPFS0
Divider
SPWM clock, Fosc=20MHz
SPWM clock, Fosc=24MHz
0
0
1
1
0
1
0
1
2
4
10MHz
5MHz
12MHz
6MHz
8
2.5MHz
1.25MHz
3MHz
16
1.5MHz
SPWM Registers - SPWM Data Register (SPWMD0, 0A4H)
bit-7
bit-0
SPWMD04 SPWMD03 SPWMD02 SPWMD01 SPWMD00 BRM02 BRM01 BRM00
Read/Write:
Reset value:
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SPWMD0[4:0]: content of SPWM Data Register. It determines duty cycle of SPWM output waveform.
BRM[2:0]: will insert certain narrow pulses among an 8-SPWM-cycle frame
N = BRM[2:0]
Number of SPWM cycles inserted in an 8-cycle frame
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
Example of SPWM timing diagram:
MOV SPWMD0 , #83H
MOV P1CON , #04H
; SPWMD0[4:0]=10h (=16T high, 16T low), BRM0[2:0] = 3
; Enable P1.2 as SPWM output pin
Specifications subject to change without notice,contact your sales representatives for the most recent information.
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Ver 2.1 SM79108 08/2006
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
