SM5953
8-Bit Micro-controller
15KB with ISP Flash
& 256B RAM embedded
Mnemonic
Description
Dir.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RST
Watchdog Timer
Watchdog timer
control register
System Control
Register
WDTC
9FH WDTE
-
CLEAR
-
-
-
-
-
PS [2:0]
-
00H
00H
SCONF
BFH
WDR
-
ISPE
ALEI
Mnemonic: WDTC
Address: 9Fh
7
6
-
5
4
-
3
-
2
1
0
Reset
00H
WDTE
CLEAR
PS [2:0]
WDTE: Watch Dog Timer enable bit.
CLEAR: Watch Dog Timer clear bit.
If CLEAR bit set to1, setting this bit the Watchdog timer counter clear and re-start to
count from the Beginning.
PS[2:0]: Watch Dog timer over flow period setting.
Mnemonic: SCONF
Address: BFh
7
6
-
5
-
4
-
3
-
2
1
-
0
ALEI
Reset
00H
WDR
ISPE
WDR Watch Dog Timer Reset.
When system reset by Watch Dog Timer overflow, WDR will be set to 1.
User should check WDR bit whenever un-predicted reset happened.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M074 Ver B SM5953 12/27/2013
- 36 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
