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SM39A16M1U32 参数 Datasheet PDF下载

SM39A16M1U32图片预览
型号: SM39A16M1U32
PDF下载: 下载PDF文件 查看货源
内容描述: SM39A16M1\n8位微控制器\n16KB具有ISP功能的Flash\n& 1K + 256B RAM的嵌入式 [SM39A16M1 8-Bit Micro-controller 16KB with ISP Flash & 1K+256B RAM embedded]
分类和应用: 微控制器
文件页数/大小: 106 页 / 1520 K
品牌: SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
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SM39A16M1  
8-Bit Micro-controller  
16KB with ISP Flash  
& 1K+256B RAM embedded  
6.2.2 Second phase: Executing calculation.  
During executing operation, the MDU works on its own parallel to the CPU. When MDU is finished, the MDUF register  
will be set to one by hardware and the flag will clear at next calculation.  
Mnemonic: PCON  
Address: 87h  
7
6
5
4
-
3
-
2
-
1
0
IDLE  
Reset  
40H  
SMOD  
MDUF  
-
STOP  
MDUF: MDU finish flag.  
When MDU is finished, the MDUF will be set by hardware and the bit will clear by  
hardware at next calculation.  
Table 6-3 MDU execution times  
Operation  
Number of Tclk  
Division 32bit/16bit  
Division 16bit/16bit  
17 clock cycles  
9 clock cycles  
11 clock cycles  
Multiplication  
Shift  
min 3 clock cycles , max 18 clock cycles  
min 4 clock cycles , max 19 clock cycles  
Normalize  
6.2.3 Third phase: Reading the result from the MDx registers.  
Read out sequence of the first MDx registers is not critical but the last read (from MD5 - division and MD3 -  
multiplication, shift and normalizing) determines the end of a whole calculation (end of phase three).  
Table 6-4 MDU registers read sequence  
Operation  
32Bit/16Bit  
MD0 Quotient Low  
MD1 Quotient  
16Bit/16Bit  
MD0 Quotien Low  
MD1 Quotien High  
16Bit x 16Bit  
MD0 Product Low  
MD1 Product  
shift/normalizing  
MD0 LSB  
MD1  
First read  
MD2 Quotient  
MD2 Product  
MD2  
MD3 Quotient High  
MD4 Remainder L  
MD5 Remainder H  
MD4 Remainder Low  
MD5 Remainder High  
Last read  
MD3 Product High  
MD3 MSB  
6.3 Normalizing  
All reading zeroes of integers variables in registers MD0 to MD3 are removed by shift left operations. The whole  
operation is completed when the MSB (most significant bit) of MD3 register contains a ‟1‟. After normalizing, bits  
ARCON.4 (MSB) to ARCON.0 (LSB) contain the number of shift left operations, which were done.  
6.4 Shifting  
SLR bit (ARCON.5) has to contain the shift direction, and ARCON.4 to ARCON.0 the shift count (which must not be 0).  
During shift, zeroes come into the left or right end of the registers MD0 or MD3, respectively.  
Specifications subject to change without notice contact your sales representatives for the most recent information.  
ISSFD-M069  
Ver C SM39A16M1 7/31/2013  
- 34 -  
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