SM39A16M1
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
The error flag is set when:
Phase
two in process and write access to mdx registers (restart or interrupt calculations)
The error flag is reset only if:
Phase two finished (arithmetic operation successful completed) and read access to MDx registers.
MDOV - Multiplication Division Overflow flag. The overflow flag is read only.
The overflow flag is set when:
Division
by Zero
Multiplication
with a result greater then 0000FFFFh
Start
of normalizing if the most significant bit of MD3 is set(MD3.7 = 1)
The overflow flag is reset when:
Write access to MD0 register (Start Phase one)
SLR - Shift direction bit.
SLR = 0 – shift left operation.
SLR = 1 – shift right operation.
SC[4:0] - Shift counter.
When preset with 00000b, normalizing is selected. After normalize sc.0 – sc.4 contains
the number of normalizing shifts performed. When sc.4 – sc.0 ≠ 0, shift- operation is
started. The number of shifts performed is determined by the count written to sc.4 to sc.0.
sc.4 – MSB ... sc.0 – LSB
6.2
Operation of the MDU
Operations of the MDU consist of three phases:
6.2.1
First phase: Loading the MDx registers.
The type of calculation the MDU has to perform is selected following the order in which the mdx registers are written to.
Table 6-2 MDU registers write sequence
16bit/16bit
16bit x 16bit
MD0 Dividend Low
MD0 Multiplicand Low
MD1 Dividend High
MD4 Multiplicator Low
MD1 Multiplicand High
MD4 Divisor Low
MD5 Divisor High
Operation
First write
Last write
32bit/16bit
MD0 Dividend Low
MD1 Dividend
MD2 Dividend
MD3 Dividend High
MD4 Divisor Low
MD5 Divisor High
shift/normalizing
MD0 LSB
MD1
MD2
MD3 MSB
ARCON start conversion
MD5 Multiplicator High
A write to md0 is the first transfer to be done in any case. Next writes must be done as shown in Table 6-2 to determine
MDU operation. Last write finally starts selected operation.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M069
Ver C
SM39A16M1
7/31/2013
- 33 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
