SM39A16M1
8-Bit Micro-controller
16KB with ISP Flash
& 1K+256B RAM embedded
6. Multiplication Division unit
This on-chip arithmetic unit provides 32-bit division, 16-bit multiplication, shift and normalize features. All operations are
unsigned integer operation.
Table 6-1 Multiplication Division Register
Mnemonic
Description
Direct
Bit 7 Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESET
Multiplication Division Unit
SMO
D
MD
UF
MD
OV
PCON
Power control
87H
EFh
-
-
-
-
STOP IDLE
40H
Arithmetic
Control register
Multiplication/
Division
Register 0
Multiplication/
Division
Register 1
Multiplication/
Division
Register 2
Multiplication/
Division
Register 3
Multiplication/
Division
Register 4
Multiplication/
Division
ARCON
MDEF
SLR
SC[4:0]
00H
00H
MD0
MD1
MD2
MD3
MD4
MD5
E9h
EAh
EBh
ECh
EDh
EEh
MD0[7:0]
MD1[7:0]
MD2[7:0]
MD3[7:0]
MD4[7:0]
MD5[7:0]
00H
00H
00H
00H
00H
Register 5
6.1 Operating registers of the MDU
The MDU is handled by eight registers, which are memory mapped as special function registers. The arithmetic unit
allows operations concurrently to and independent of the CPU‟s activity. Operands and results registers are MD0 to
MD5. Control register is ARCON. Any calculation of the MDU overwrites its operands.
Mnemonic: ARCON
Address: EFh
7
6
5
SLR
4
3
2
1
0
Reset
00H
MDEF MDOV
SC[4:0]
MDEF- Multiplocation Division Errot Flag.
The MDEF is an error flag. The error flag is read only. The error flag indicates an improperly performed
operation (when one of the arithmetic operations has been restarted or interrupted by a new operation).
The error flag mechanism is automatically enabled with the first write to MD0 and disabled with the
final read instruction from MD3 multiplication or shift/normalizing) or MD5 (division) in phase three.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M069
Ver C SM39A16M1 7/31/2013
- 32 -
SYNCMOS [ SYNCMOS TECHNOLOGIES,INC ]
