HV461
Block Diagram and Typical Application
C
DC
100nF
R
DC1
R
DC2
R
DC3
R
DC4
R
FB1
30.1k
COM
P2
D
IFFAMPO
DIFFAMP-
DIFFAMP+
Error
Amplifier
Differential
Amplifier
R
TSYNC
and C
TSYNC
selected for
desired ring sync lead time
R
TSYNC
3.3k
VREF2
R
DC1
- R
DC4
selected for
the desired DC Offsets.
R
COMP
2.7k
C
COMP2
1nF
C
SINE
47nF
VREF1
C
TSYNC
100nF
TSYNC
SYNC
SINEREF
DCREF1–3
Offset
Mux
VREF1
+1
sync
clk
Sine Wave
freq
C
COMP1
47nF
COMP1
R
FB2
4.02M
R
FB4
4.02M
Y
1
19.6608MHz
XTAL
Sync
OSC
20k
20k
20k
40k
VREF1
Latch
Transparent Latch
freq
am
p
offset
2
2
VREF1
2
20k
10k
R
FB3
30.1k
V
REF1
ringer
output
output
reference
refer to
power stage
schematic
Synthesizer
reset
3
external ring
frequency
R
PLL
PLL filter only required for
10k
external ring frequency
C
PLL2
33µF
V
GD
FRING
PLLFLT
Amplitude
Mux
+1
10k
PLL
PWM
Controller
switch
drivers
PWM
in
SW
1
SW
2
SW
3
SW
4
C
PLL1
4.7µF
FREQ0
FREQ1
FREQ2
AMP0
AMP1
OFF0
OFF1
ENABLE
LE
referto power
stage schematic
HV461FG
enable
curren
t
limit
CL+
CL-
CLCOMP
V
REF1
PWMSYNC
R
OSC
to host
controller
osc
enable
Enable
Control
dutycyclelimit
overrange
overcurrent pri deadband
sec delay
VDC
L
TD
B
TD
LY
R
OSC
267k
V
DD
R
DCL1
100 k
Ω
R
DCL2
33 k
Ω
V
DD
R
DB
4.7 k
Ω
C
DB
120pF
V
DD
V
DD
SYNCMODE
R
DLY
4.7 k
Ω
1.25V
VREF1
VREF2
Precision
2.50V
Reference
undervoltage
Deglitcher
CFAULT
C
DLY
selected for
desired Fault
response time
C
FAULT
10µF
V
DD
C
DLY
120pF
C
REF1
100nF
C
REF2
100nF
V
DD
10 A
Undervoltage
D
etector
FAULT
Boost
C
onverter
AVD
D
DVD
D
VDR
VGD
AGND
D D
GN
PGND
R
FAULT
100 k
Ω
RESET
to host
controller
C
RESET
4.7µF
L
GD
330µH
V
D
D
D
GD
4148
C
GD
6.8µF
C
DD1
10µF
C
DD2
100nF
Q
GD
TN
2504
Figure 5: Block Diagram and Typical Application
9
SUPERTEX [ Supertex, Inc ]
