HV461
12 CFAULT
A capacitor from this pin to ground sets the integration time of the FAULT detection circuitry. A larger capacitor
provides less suseptability to transient problems, while a smaller capacitor provides quicker response. Values
in the range of 1µF to 100µF are appropriate. If the FAULT output is not used, this pin should be grounded.
See also FAULT (pin 15).
13 SYNCMODE With SYNCMODE low, ringer output ceases the instant ENABLE goes low. When high, ringer output ceases at
the next ring signal phase crossing (0º/180º) after ENABLE goes low.
14 SYNC
Outputs a pulse indicating sine reference 0º and 180º phase crossing (not to be confused with zero–voltage
crossing). The rising edge precedes phase crossing by a user–adjustable time period (see TSYNC pin 44).
Falling edge coincides with sine reference phase crossing. SYNC is digitally derived, therefore phase shifts
caused by the external filter capacitor at SINEREF will not be reflected at the SYNC output.
Indicates abnormal operating conditions of output overcurrent, supply undervoltage (VDD & VGD), or PWM
overrange (duty cycle limit – see VDCL, pin 3). Together, these 3 conditions catch most any problem. When an
overcurrent or overrange condition exists for more than 8% of the time, this output becomes active. It is cleared
when the problem occurs less than 2% of the time. Undervoltage conditions immediately activate the FAULT
output. It is active low and open drain to allow wire-ORing. See CFAULT (pin 15) for additional information.
15 FAULT
Ringer output enable. Active high. When enabled, the ring signal always starts immediately at 0 degrees. If
AMP≠00, SW1 and SW2 are held off when ENABLE=0 but SW3 and SW4 continue switching. If AMP=00, SW3
and SW4 are held off as well. When disabled, the error amplifier is set at unity gain to prevent saturation,
reducing turn-on glitches when re-enabled. See SYNCMODE (pin 13) for additional information.
16 ENABLE
17 OFF0
Sets ring DC offset. Offset changes are effected at the next phase crossing (0º/180º) of the ring signal. Except
for 00, offsets are set by the voltages at DCREF1–3. (OFF0 is LSB) Offset = ½ x Gain x (VDCREFx - VREF1
)
18 OFF1
19 AMP0
00 = 0V
01 = DCREF1
10 = DCREF2
11 = DCREF3
Sets ring amplitude. Amplitude changes are effected at the next phase crossing (0º/180º) of the ring signal.
Amplitudes, as a percentage of full scale, are: (AMP0 is LSB) Full scale amplitude = 0.707VRMS x Gain
20 AMP1
00 = 0%
01 = 50%
10 = 75%
11 = 100%
Sets ring frequency. Frequency changes are effected at the next phase crossing (0º/180º) of the ring signal.
Frequencies when using a 19.6608MHz crystal are: (FREQ0 is LSB)
21 FREQ0
22 FREQ1
23 FREQ2
000 = 16.7Hz
100 = 33.3Hz
001 = 20Hz
101 = 40Hz
010 = 25Hz
110 = 50Hz
011 = 30Hz
111 = 60Hz
Latch enable. The latch gates control inputs FREQ0–2, AMP0–1, OFF0–1, and ENABLE. When LE is high,
latch outputs follow inputs. On a low–going transition, outputs are latched.
24 LE
25 TDLY
An RC network on this pin sets the primary to secondary switch delay. This prevents the secondary–side
switches (SW3&4) from turning on prematurely. tDLY=0.48RC
26 TDB
An RC network on this pin sets the deadband (break–before–make time) on the primary–side switches
(SW1&2). Deadband prevents both switches from conducting simultaneously. tDB=0.48RC
27 DGND
28 SW4
29 SW3
Digital ground. Connect to AGND and PGND close to the IC.
Secondary–side switch driver output.
Secondary–side switch driver output.
30 SW2
31 SW1
32 PGND
33 VGD
Primary–side N-channel switch driver output.
Primary–side P-channel switch driver output.
Power ground. Connect to AGND and DGND close to the IC.
Supply for the SW1–4 drivers. An external boost converter controlled by VDR provides 9.6V for driving the
power stage MOSFETs. An undervoltage condition on this supply pin disables ringer output and activates the
FAULT output.
34 VDR
35 DVDD
36 CL+
Gate drive for the external boost converter circuit. Outputs a fixed 50% duty cycle at the ringer PWM frequency
(see ROSC, pin 9). Output voltage regulation is via burp-mode operation. This output is boostrapped to VGD,
thus during startup VDR amplitude is VDD and after startup is VGD. (See VGD, pin 33)
Supply for the digital section. 3.0V to 3.6V input. Undervoltage disables ringer output. Must be from the same
source as AVDD. Bypass with a 100nF capacitor to ground as close as possible to the IC. An undervoltage
condition on this supply pin disables ringer output and activates the FAULT output.
Current limit amplifier non-inverting input.
12
SUPERTEX [ Supertex, Inc ]
