HV110
PWRGD
Description of Operation
The PWRGD (active low) pin is an open drain active low
MOSFET, (referred to VNN) which is enabled when the gate
voltage on the internal power MOSFET reaches its full on
voltage, provided that the slew rate (VSLEW) timeout for large
capacitor is not being used.
Signature Detection
During the Discovery process, the PSE applies a voltage
as described in the Discovery section on page 4 and de-
termines if there is a PD connected at the other end of the
cable. The power loss across the 25KΩ signature resistor
will be less than 120mW - less than 1% of the power de-
livered to PD. It is therefore not critical to disconnect the
signature resistor after the PD detection. However, this can
be easily accomplished by using a low cost bipolar transistor
and resistors. Note that the resistance of the external circuit
connected between the DRAIN and VPP pin of the HV110
should be greater than 500kΩ (in the 2.8 – 10V Discovery
voltage range) for the signature detect to work properly (usu-
ally the case with active loads like DC-DC converters).
Any fault condition will return PWRGD to a high impedance
state, turning off the HV110 and the DC/DC converter. The
PSE will also detect an undercurrent condition for a period
greater than 350ms (nominal), and will shut down by itself. It
will then wait for the next Discovery cycle.
Programmable UVLO and Hysteresis
ULVO is internally set through a 2.5MΩ and 116K resistance
divider in the HV110. The default values of UVLO are given
in the Electrical Characteristics on page 2.
Because of the Zener diode connected to VPP pin, it will be
necessary to modify the internal UVLO thresholds by using
two external resistances as shown in pages 1, 9 and 10,
to provide the UVLO turn-off and turn-on voltages to meet
the IEEE 802.3af standard. These two resistors perform dual
functions, UVLO voltage adjustments and also the Signature
Detection function (i.e. represent the 25k impedance). Page
9 shows a different implementation using a PNP transistor
which allows the use of the HV110’s internal UV circuit.
The UVLO circuit has a built in Hysteresis of 8.0V, to enable
stable operation during a UV condition. See the section on
Signature Detection for further details.
Internal MOSFET with Current Mirror
The HV110 includes an internal 90V, 1.0Ω MOSFET. The
MOSFET current is mirrored to a current detect circuit with-
in the chip, utilizing a proprietary Supertex algorithm and
wastes almost no power. Elimination of a sense resistor,
necessary with external power switches, means additional
energy savings, providing higher power output. Use of an
on-board FET and the thermal supervisor also leads to high
reliability compared to ICs that use external FETs whose
temperatures cannot be easily monitored.
Once the voltage exceeds 12V, the HV110 will turn on and
begin drawing a quiescent current of 1mA typical.
Current Limit Functions
The HV110 monitors the drain voltage and the current in the
load switch. During initial inrush if the drain does not move
more than 90% of input voltage within a short-circuit timer
period (tSC = 60ms), then the device will conclude that a short
circuit condition exists, will turn off the internal FET and try
to auto-restart after a period of 9 seconds. If the initial inrush
period ends within this period as per the IEEE802.3af stan-
dards then the internal FET is turned fully on to minimize its
on resistance and the PWRGD pin will be pulled low, to the
negative rail.
PD Polarity
According to IEEE802.3af, PD shall be insensitive to the po-
larity of the power supply and shall be able to operate in
Mode A and Mode B (cases when the power is transferred
through the signal leads and spare leads). The connections
to the 8-pin modulator jack are different for ModeAand Mode
B, polarity on the pins can be different for Mode A.
Accommodating the different pin combinations and polar-
ity are beyond the scope of the PD Controller IC, however
these must be taken care of in the system design. One of
the ways of ensuring the polarity protection is to use a small
bridge rectifier in between the 8-pin connector terminal and
the PD Controller.
Figure 1 shows the turn on sequence of the HV110. Once
Discovery is complete, the PWRGD will be high impedance.
After the optional Classification is complete and UVLO is
satisfied, the HV110 will provide a controlled turn on of the
internal switch (90V, 1W Power MOSFET), limiting the in-
rush current maximum value of 350mA (nominal).
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SUPERTEX [ Supertex, Inc ]
