HV110
Classification Circuit with the HV110
CPORT
+
12V
Optional
DC/DC
Converter
3.3/5V
VPP
PHY
UVLO/
ENABLE
PWRGD
ENABLE
HV110
DRAIN
VNN
Alternate Method for Powering the HV110
The 12V Zener diode connected to the VPP pin of the HV110 Figure 10 shows the modified circuit. In the Discovery stage,
(shown in Figure 1) is required to block the IC in the Discov- the input voltage is less than 10V. This causes the Zener
ery process, so that the quiescent current of the IC does to be reverse biased and hence there is no base current to
not interfere with the signature resistance detect. However, the PNP transistor. Once the input voltage increases beyond
this Zener causes a 12V drop across it, causing the HV110 12V, the Zener starts conducting, which provides a base cur-
to see only 36V. This makes the internal UV thresholds un- rent path for the PNP transistor. The transistor goes into the
usable. By using a PNP transistor along with a low power saturation region, essentially pulling VPP to the rail.
Zener and resistor instead, the built-in undervoltage thresh-
olds can be utilized.
Powering the HV110 using a PNP transistor instead of a Zener
10kΩ
CPORT
+
DC/DC
Converter
3.3/5V
20kΩ.
1/4W
24.9kΩ
VPP
PHY
UVLO/
ENABLE
PWRGD
ENABLE
0.47µF
HV110
12V
350mW
DRAIN
VNN
9
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