HV110
Input Current
DRAIN
I
nput Voltage
PWRGD
Figure 3. Auto-restart into a shorted output
Figure 1. Turn-on waveforms of the HV110
DC Disconnect
During regular operation a fault condition can occur. The
HV110 includes a current monitor that continuously watches
the FET current. If the current exceeds 350mA (nominal),
fast-return to limit feature will be activated and the over-cur-
rent limit circuit will limit the output current to 350mA (nomi-
nal), as shown in Figure 2.
The HV110 includes an under-current detection circuit to
disconnect the PD when the current falls below the under-
current threshold level. The HV110 will turn the internal FET
off if the load current falls below a threshold level of 10mA
(nominal) for a period determined by the under-current timer
(signature drop-out time, tUC 350ms nominal). In Class 0 ap-
plications, this acts as an additional protection to help over-
come rapid reinsertion of a legacy or non-compliant device.
Input Current
DRAIN
The HV110 provides most of the safety and timing require-
ments of a PSE in PoE applications hence can be considered
as a secondary/redundant stage to comply with the IEEE
802.3af standards for the powered device. One motivation
for this is that the PSE is an unknown quantity and may not
be fully IEEE802.3af compliant in all cases. The HV110 will
ensure that valuable PD devices are not damaged and that
they fulfill the IEEE802.3af compliance.
Input Voltage
PWRGD
Turning on to a large CPORT
The PSE is required to limit the start up currents for CPORT
less than 180mF only, as per the IEEE802.3af standard. For
higher value of CPORT, the powered device has to limit the
current. Figure 5 shows that the HV110 limiting current into
300mF as required by the IEEE802.3af specification.
Figure 2. PD Current jumps from 200mA to 400mA,
Controller shuts down in 60ms
To allow charging of extremely large capacitors, the HV110
includes a feature that will disable the turn on timers, PWRGD
and Time out. This feature is based on the turn on voltage
slew rate (VSLEW). If VSLEW is kept below 4.25V/ms then the
timers are disabled and limiting will occur indefinitely until
CPORT is charged. This will also, however, disable PWRGD
that is enabled by the same timer. In most cases the capaci-
tor used in powered device application is well below 180µF
so this feature is not of much significance in a powered de-
vice application.
If the fault is not cleared within the nominal over-current timer
limit of 60ms, the HV110 will turn off the pass element, and
initiate an auto-restart sequence, with a 9 second interval as
shown in Figure 3. In the event the over-current is cleared
before the over-current timer has expired, then the over-cur-
rent timer will be reset and the device will start to function
normally.
7
SUPERTEX [ Supertex, Inc ]
