SMM764
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
sequence position. Any unused channel should be
assigned to the null sequence position.
registers provide the real-time status of all monitored
inputs.
The voltage threshold limits for inputs VMA-D, VDD and
12VIN can be programmed to trigger the RST# and
HEALTHY outputs as well as a Fault-Triggered force-
shutdown and power-off operation when exceeded.
The threshold limits for the internal temperature
sensor and the AIN1 and AIN2 inputs can be
programmed to assert the RST#, HEALTHY, and
FAULT# output pins
The HEALTHY and FAULT# outputs of the SMM764
are active as long as the monitored threshold remains
in violation. The RST# output also remains active as
long as the monitored threshold remains in violation.
However, once the threshold violation goes away, the
RST# will remain active for a programmable reset
timeout period (tPRTO).
The SMM764 treats Command-Triggered force-
shutdown and power-off operations, those caused by
I2C commands and assertion of the FS# and
PWR_ON pin, differently than those caused by a
Fault-Triggered forced-shutdown and power-off
conditions, those caused by UV/OV violations or a
sequence termination timer expiration. The mode in
which either a forced-shutdown or a power-off occurs
effects how or whether the SMM764 will restart, and
the number of allowable retries permitted.
ONGOING OPERATIONS-MONITORING MODE
During ongoing operations mode, the part can monitor,
and actively control via ADOC, and use the force-
shutdown operation if necessary.
Once the power-on sequence is complete, depending
on the user programmed settings; the SMM764 will
either enter the ongoing operations mode directly or
wait for ADOC to successfully bring all channels within
their nominal values. The ongoing operations mode
will end when a power-off sequence, or force-
shutdown has been initiated.
Once the ongoing operations mode has begun, the
SMM764 continues to monitor all VMX inputs, the VDD
and 12VIN inputs, and two temperature sensor inputs
with a 10-bit ADC. Each of these inputs is sampled
and converted by the ADC every 2ms. The ADC input
has a range of 0V to four times the voltage on VREF
for inputs VMA-D and the VDD input. The range is
extended to 12 times VREF for the 12VIN input and is
reduced to two times VREF for the AIN1 and AIN2
inputs.
The SMM764 monitors internal temperature using the
10-bit ADC and the automonitor function. Two under-
temperature and two over-temperature thresholds can
be set, each with its own programmable threshold
options and consecutive conversion, before trigger
counter. Resolution is 0.25 C per bit scaled over the
range of -128 C to 127.75 C. The temperature value
can be acquired over the I2C bus as a 10-bit signed
two's complement value.
TEMPERATURE SENSOR ACCURACY
The internal temperature sensor accuracy is ±5oC from
-40 to +85oC. The sensor measures the temperature
of the SMM764 die and the ambient temperature. If
VDD is at 5V, the die temperature is +2oC and at 12V,
it is +4oC. In order to calculate this difference in
specific applications, measure the VDD or 12VIN
supply current and calculate the power dissipated and
multiply by 80oC/W. For instance, 5V and 5mA is
25mW, which creates a 2oC offset.
The SMM764 compares each resulting ADC
conversion with two programmable 10-bit under-
voltage limits (UV1, UV2) and two programmable 10-
bit over-voltage limits (OV1, OV2) for the
corresponding input.
A consecutive conversion
counter is used to provide filtering of the ADC inputs.
Each limit can be programmed to require 1, 2, 4 or 6
consecutive out-of-limit conversions before it is said to
be in fault. One in-limit conversion will remove the
fault from the threshold limit. This provides digital
filtering of the monitored inputs. The ADC inputs VMA-D
can use additional filtering by connecting a capacitor
from the corresponding CAPX pins to ground to form
an analog RC filter (R=25kΩ). The input is considered
to be in a fault condition if any of its limit thresholds
are in fault. Setting an OV threshold limit to full-scale
MARGINING
The SMM764 has two additional ADOC voltage
settings for channels A-D, margin high and margin
low. The margin high and margin low voltage settings
can range from 0.3V to VDD of the converters’
nominal output voltage, depending on the specified
margin range of the DC-DC converter.
These
settings are stored in the configuration registers and
are loaded into the ADOC voltage setting by margin
commands issued via the I2C bus. The channel must
be enabled for ADOC in order to enable margining.
The margin command registers contain two bits for
(3FFHEX), or setting a UV threshold limit to 000HEX
,
ensures that the limit can never be in fault. The status
Summit Microelectronics, Inc
2098 1.1 6/29/2005
16
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
