SMM665B
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
S
T
S
T
A
Command and Status
Register Address
R
O
P
Master
Slave
Bus Address
Data
T
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
D
3
D
2
D
D
0
1
0
0
1
W
4
1
A
C
K
A
C
K
A
C
K
Figure 25 – Command and Status Register Write
S
T
S
T
A
R
T
A
Command and Status
Register Address
R
Master
Slave
Bus Address
Bus Address
T
A
2
A
1
A
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
2
A
1
A
0
1
0
0
1
W
1
0
0
1
R
A
C
K
A
C
K
A
C
K
N
A
C
K
S
T
A
C
K
A
C
K
O
P
Master
Slave
Data (1)
Data (n)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Figure 26 - Command and Status Register Read
S
T
S
T
A
R
T
A
R
Master
Slave
Bus Address
Channel Address
Bus Address
T
C
H
3
C
H
2
C
H
1
C
H
0
A
2
A
1
A
0
A
2
A
1
A
0
1
0
0
1
W
0
0
0
0
1
0
0
1
R
A
C
K
A
C
K
N
A
C
K
S
T
N
A
C
K
S
T
A
R
T
A
C
K
O
P
Master
Slave
Bus Address
Channel Address Echo
10-Bit ADC Data
C
H
3
C
H
2
C
H
1
C
H
0
A
2
A
1
A
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
0
0
1
R
0
0
A
C
K
Figure 27 – ADC Conversion Read
Summit Microelectronics, Inc
2089 1.1 10/20/04
27
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
