SMM153
I
2
C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100kHz
T
A
= 0°C to +70°C, VDD = 2.7V to 5.5V unless otherwise noted. All voltages are relative to GND. See Figure 3 Timing
Diagram.
Symbol
f
SCL
t
LOW
t
HIGH
t
BUF
t
SU:STA
t
HD:STA
t
SU:STO
t
AA
t
DH
t
R
t
F
t
SU:DAT
t
HD:DAT
TI
t
WR
Description
SCL Clock Frequency
Clock Low Period
Clock High Period
Bus Free Time
Start Condition Setup Time
Start Condition Hold Time
Stop Condition Setup Time
Clock Edge to Data Valid
Data Output Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Data In Setup Time
Data In Hold Time
Noise Filter SCL and SDA
Write Cycle Time
Conditions
Min
0
4.7
4.0
Typ
Max
100
Units
KHz
μs
μs
μs
μs
μs
μs
Before New Transmission, Note 5
4.7
4.7
4.0
4.7
SCL low to valid SDA (cycle n)
SCL low (cycle n+1) to SDA
change
Note 5
Note 5
0.2
0.2
3.5
μs
μs
1000
300
250
0
ns
ns
ns
ns
Noise suppression
100
5
ns
ms
Note 1:
V
HYST
is measured with a 1.25V external voltage and is determined by subtracting Threshold Low from Threshold High, V
TH
-V
TL
while monitoring
the FAULT# pin state. Actual DC Hysteresis is derived from the equation: (V
IN(COMP1/2)
/V
REF
)(
V
HYST
). For example, if V
IN(COMP1/2)
/=2.5V and V
REF
=1.25V then
Actual DC Hysteresis= (2.5V/1.25V)(0.003V)=6mV.
Note 2: Current sense accuracy depends on the current sense resistor tolerance. Kelvin sensing of the voltage drop across this resistor must be used to
guarantee accuracy. Accuracy at the low range of the current monitor ADC will be adversely impacted by offset errors.
Note 3: It is recommended that ADC reads occur with a frequency of not more than 250Hz.
Note 4: Voltage accuracy is only guaranteed for factory-programmed settings. Changing voltage from the value reflected in the customer specific CSIR
code may result in inaccuracies exceeding those specified above.
Note 5: Not 100% Production tested. Guaranteed by Design and/or characterization.
Note 6: All electrical parameters are guaranteed to function over the stated VDD, VCS and temperature range. Electrical parameters not specified as
"guaranteed by design" are tested with a VDD voltage required of the specific application. For example, if the device is to be operated at 3.3V and VCS
supply of 12V, it is tested with a VDD supply of 3.3V, +-10% and a VCS supply of 12V, +-10%.
TIMING DIAGRAMS
t
HIGH
t
WR (For Write Operation Only)
t
LOW
t
SU:DAT
t
SU:STO
t
BUF
t
R
SCL
t
SU:STA
SDA
(IN)
t
AA
SDA
(OUT)
t
F
t
HD:STA
t
HD:DAT
t
DH
Figure 3. Basic I
2
C Serial Interface Timing
Summit Microelectronics, Inc
2134 3.0 1/20/2010
7
SUMMIT [ SUMMIT MICROELECTRONICS, INC. ]
