SMM153
INTERNAL BLOCK DIAGRAM
VREF
FAULT#
VDD
VDD_CAP
GND
COMP1
COMP2
OV/UV
OV/UV
0.5V/1.25V
VREF
Glitch
Filter
Output
Control
VREF = 1.25V
50kΩ
A0
A1
A2
SCL
SDA
I2C
Interface
WP
Clock
MUX
10-Bit
ADC
CAPM+
CAPM-
EE
GPIO0
GPIO1
GPIO2
GPIO3
25kΩ
25kΩ
Configuration
Registers
& Memory
Control
Logic
VM+
VM-
CAPC
CS+
250kΩ
DIFF
AMP
CS-
Figure 2 – SMM153 Controller Internal Block Diagram.
PACKAGE AND PIN CONFIGURATION
28-Pad 5x5 QFN
Top View
Pin 1
23
28 27 26 25 24
22
1
21
20
19
SCL
VDD
N/C
COMP1
CS+
CS-
CAPC
VM-
2
3
A2
GPIO0
A1
GND
A0
SMM150
4
5
6
7
18
17
16
15
GND
9
10 11
13 14
12
8
Summit Microelectronics, Inc
2134 3.0 1/20/2010
3